Oh we do:
https://www.anandtech.com/show/16150/amd-teases-radeon-rx-6000-card-performance-numbers-aiming-for-3080
Pieces of a puzzle, several known data miners are never wrong together? Or :runaway:
It is true that we never know anything, it is just multi-subjectively agreed upon realities...
For Nav21 speculation that is missing the point though, what is interesting is that we now know that the 6800XT is minimum 10k+ points @ FSU. Which means that the 6900XT is probably ~10-15% faster so approx, 11-12.5k points for FSU performance. But purely conjecture.
There is a comment in the...
Residency map descriptors
Document Type and Number:
United States Patent 1054080
Filing Date: 01/31/2019
Publication Date: 01/21/2020
Abstract:
A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at...
I agree. The only reasonable chance of a big RDNA1 chip would be in devkits for internal usage at Microsoft and AMD I'd think at this point. Microsoft wouldn't care paying for a few wafers to get early access to their Xbox series X chip even if at 1/3 to 2/3 speeds of final product.
Just putting an idea out there - Microsoft surface family, specifically studio 2 is running old hardware. A Ryzen 3700 Pro with 5600 XT or Navi12 for NUC form factor. Sounds almost like a devkit for Project Scarlet :runaway:
Can they be decoupled from two (16+16-bit) channel though, from any practical standpoint? As far as I've read on GDDR 6 they can't, they can be joined in pseudo channel mode with penalty. But I am not an engineer by trade. So even if one channel is 16-bit, the bus-width of the controller to the...
192-bit bus mean 6x 32 bit GDDR6 memory controllers. Highly likely there is a 30 CU part in the 5600-series, but if the 5600-series is a cut down Navi 10 e.g. Navi10LE it could go as high as 36 CU in steps of two, though unlikely. From a business prospective I doubt 36 CU due to cannibalization...