Recent content by Mat3

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    AMD RX 7900XTX and RX 7900XT Reviews

    Also, when it can't dual issue from the same wavefront, why can't they make it so that it could fill the other ALU from another wavefront that is ready to go? Seems like a no-brainer at a high level, so there must be some difficult technical hurdle to overcome to make it work.
  2. M

    AMD RDNA3 Specifications Discussion Thread

    The Anandtech article briefly mentions it. While we’re on the subject of AMD’s L3 Infinity Cache, it’s notable here that it’s actually a bit smaller on Big Navi 3x than it was on Navi 21, with a maximum capacity of 96MB versus 128MB on the former. According to AMD they’ve made further...
  3. M

    AMD RDNA3 Specifications Discussion Thread

    On the SIMDs, is there any idea here on how often it will dual issue ? I mean vaguely of course. I assume it's most of the time or it would hardly seem worth it. Is wave32 the norm? How can wave64 do any type of operation across all the ALUs, but in wave32 mode half the ALUs can do only floats...
  4. M

    AMD RDNA3 Specifications Discussion Thread

    Why not put the ROPs on the MCDs as well? Dont' they usually benefit from being as close as possible to the cache and memory? Or maybe that's the L2 cache. I'm thinking back to the Xbox 360 GPU design.
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    AMD RDNA3 Specifications Discussion Thread

    This is nonsense.
  6. M

    AMD RDNA3 Specifications Discussion Thread

    When they say "dual issue", do they mean extracting ILP like back in the VLIW days?
  7. M

    AMD RDNA3 Specifications Discussion Thread

    Yeah, but that and AMD's MI250X aren't for gaming.
  8. M

    AMD RDNA3 Specifications Discussion Thread

    This let's them offload some of the big area stuff (that doesn't scale as well) that was previously on right on the GPU, which allows for more of the other stuff than would otherwise be possible. This design was also rumored for a long time, so not a surprise for most. Separating the main GPU...
  9. M

    AMD RDNA3 Specifications Discussion Thread

    Errr, that's it!? Where's the block diagram? Where's the detailed look of the new compute units?
  10. M

    AMD: RDNA 3 Speculation, Rumours and Discussion

    More SIMDs in a workgroup processor.
  11. M

    AMD: RDNA 3 Speculation, Rumours and Discussion

    Yeah, I've wondered along those lines too. The expected design for the high end is a big GPU surrounded by 6 chiplets which house L3 cache and memory controllers and PHYs, all sitting on an interposer. So, 6 chiplets + 24GB* Gddr6 versus 16GB HBM2 (not sure HBM3 is ready enough). * I think...
  12. M

    Intel XeSS anti-aliasing discussion

    So not even using the packed math capability in VEGA and RDNA1 it seems. Those are some awful results all around. Edit: Is DP4a just 4X8? I remember the Vega whitepaper said it was capable.
  13. M

    Unreal Engine 5, [UE5 Developer Availability 2022-04-05]

    I would have thought they could make use of both at the same time, like use the software path for the general lighting and shadows but hardware ray tracing for a few surfaces with sharp reflections of moving characters (like street level windows), so that's disappointing.
  14. M

    AMD: RDNA 3 Speculation, Rumours and Discussion

    How did it work with VLIW? Was just one of the ALUs in a set fatter and capable of 64-bit? I thought they somehow combined multiple ones to make it work, like how a RDNA 32-bit ALU can do 2X16.
  15. M

    AMD: RDNA 3 Speculation, Rumours and Discussion

    As mentioned above, to arbitrarily control it by forcing FP64 operations to go to dedicated units. Do games (graphics or compute workloads) ever need it? Or it's strictly for non-gaming applications? Do the consoles have dedicated FP64 units?
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