Recent content by Homeles

There is a baseline level of circuitry that these GPUs use for things like PCI-E and display output that have nothing to do with the GPU's performance. A larger GPU will have higher areal efficiency than a smaller one from the same family, unless design decisions are made that would...

Anyway, I think he was just trying to see if he could fool a few people. There's some guys over there pumping Tegra K1 like it's the second coming of G80 or something. Are you aware of any publicly available real die photos? I'd really like to see it. Heck, I wasn't even aware there was a real...

I'm sure he'll come back saying he was playing along :wink:

Are those CPU cores actually to scale on their public "die shot," if you can even call it that? Nvidia obfuscates and doctors their Tegra die shots so heavily, that I can't help but feel like you've wasted your time. GPU "cores" simply don't look like that in any GPU image I've ever seen. In...

More units don't necessarily mean more power. If that were the case, GPUs would be few-core and run at a high frequency. Really, at least at the frequency ranges GPUs operate at, more CUs = less power at a given performance level. I'm really confused why you're asserting the opposite, when...

That doesn't invalidate his point.

This does make sense though... they're risk, or even pre-risk production yields. Nothing out of the ordinary here. The only interesting bit this yield information gives us, assuming that it's true, is that Samsung's 20nm node is a few months behind TSMC's, which shouldn't surprise anyone...

Aren't these typical early-life yields? They still have several months to go before volume manufacturing begins, and even then, it's going to be early volume manufacturing where wafers are scarce, prices are high, and deisgns are few. By the end of the year, TSMC will likely be yielding more...

They're pretty massive at low voltage. Performance wise, Intel blows everything out of the water.

I understand that power is a problem. That's the entire point of my original post. Had you read it, you might have avoided this whole issue.

No, it did not. Let me hold your hand (again): Here, I am asking if it is necessary to expand cache sizes to support 512-bit AVX. This question has remained unanswered. Also, note the absence of anything related to power in my question here. Again, note the absence of anything power related...

Intel's not worried about the server market. Sorry, but that doesn't have anything to do with what I was asking.

I know that it's not their only goal, however my point is that such a move would likely take up a pretty significant portion of the transistor budget. Granted, they have a LOT of die real estate to play with, given how incredibly tiny they've made their processors over the past few generations...

Don't the goals of 512-bit AVX run counter to creating a better mobile chip? I would think that Intel would prioritize other things with their transistor budget -- a larger GPU, integrating more -- or all -- of the PCH, perhaps greater optimization for power over performance... In addition...

I'm pretty sure he was talking about the consumer models. Man, it'd be really nice to see core counts taking off.