Recent content by Gipsel

This just reminded me of an old discussion about terminology from 2011 (!) where this was said: :LOL: Sorry for the flashback.

Isn't it 0.3pj/bit for the old EMIBs with 55µm pitch and 0.15pj/bit for Lakefield and PonteVecchio (Foveros)? I guess one can always make it worse. For comparison, AMDs direct/hybrid bonding approach for der 3DVcache allegedly needs just 0.05pJ/bit.

The picture of the "Infinity links with High Performance Fanout" showing clearly translucent layers increases my suspicion, that AMD does not use elevated fan-out bridges as first reported by some outlets, but indeed some InFO-R variant without a local silicon interconnect. It enables a way...

But this slide is not from the RDNA presentation but the CDNA2 one. I know that some tech sites claim that EFBs are used, but I have not seen AMD saying it (neither in the RDNA3 slides nor the presentation). But the Anandtech article sounds like AMD told them about the EFBs basically as...

The image in the press deck is pretty blurry, but the cache portion is significantly smaller than that. I brightened it a bit: I would estimate around a 44% ratio of the total cache part (so not just the SRAM arrays) of the 37mm² for the MCD making it maybe ~16mm². Where did you see that? Is...

Actually, if you look at the pictures with the right lighting, one can see there is almost no space left at all. ;)

0.5mm may be a rule of thumb if one does a very crappy measurement with a caliper and measures not just the die but includes some underfill "leaking" out of the sides of the die in the measurement. 0.5mm is way too much for the necessary dicing strait/scribe line width between dies. More common...

I agree with your first set of numbers for GCD and MCD (they are very close to the ones Angstronomics told us a while ago [305mm² and 37.5mm², respectively]). But what is the "molding overhead" supposed to be? The visible edges of the dies in the mold are the real edges of the dies as cut from...

MI250X was basically expressly designed for high efficiency FP64 performance. There it delivers (it clocks higher and basically doubles FP64 performance [in some cases with matrix ops it quadruples it] at the same power consumption and does so while spending only a few transistors more and with...

CDNA2 is a disaster? How exactly do you come to that conclusion? Just looking at the Top500 list, I see there a system with CDNA2 accelerators sitting comfortably in the top spot. It delivers >7x the performance of the best nVidia equipped system at only twice the power consumption...

For cost efficiency one wants to reuse the MCD die across all models. An increase of the MCD integrated cache that appears to be justifiable if one looks solely at N31, may not be looking very appealing for smaller models. But on the other hand, the price AMD can achieve for the fastest version...

Well, the number of banks available for DST, SRC0, SRC1, and SRC2 operands (where no conflict is allowed between X and Y components of a VOPD instruction) are 2, 4, 4, and 2, respectively. The operand collection probably can't read arbitrarily from all register file banks (subsets of banks are...

I would look at the allocation granularity for hints (which has grown by a factor 2 from RDNA1 to RDNA2 and will go up an additional +50% [3 times that of RDNA1] with N31/N32). How do you do register allocation that is both relatively easy to do and has also the property of maintaining an equal...

Well, with a +50% increase of total register space, something should go up by 50%. How many choices do we have?

The latest LLVM patch confirms the increased register size for N31/N32. And it also says that the allocation granularity went up by 50% (24/12 vGPRs in Wave32/64 mode instead of 16/8 vGPRs or 8/4 vGPRs with RDNA1). This implies also 50% more register banks (instead of larger banks) and therefore...