Predict: The Next Generation Console Tech

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Yield is lower to start and fab house has to recoup cost of developing process plus higher demand with less volume means higher pricing.

Consoles normally move to smaller processes at a slower rate then the PC sector does so there would be very little if any costs to recoup on what would be a well established process.
 
Consoles normally move to smaller processes at a slower rate then the PC sector...
Because they wait until it's cheaper, which is what anexanhume is saying. ;) If there weren't cost issues in shifting process, consoles would move as quickly as they could to benefit from the savings.
 
Multi-processor and multi-GPUs... Is it something like the "APU+GPU" idea? :?:
If it would be true that "We know everything about multi-graphics card solutions", why do we have this crappy AFR solutions?
Indeed if you are willing to produce a quiet big chip, 250mm^2, I wonder if the most cost efficient solution is, going by your figures, to simply discard all the others elements and do with the 250 mm^2 chip alone. That would translates into a 50mm^2 CPU with a 200mm^2 integrated CPU.
That barely giving away 20% of the GPU.

The issue is that is still significantly costlier to produce a 250mm^2 than 190mm^2 and tinier ones. I'm always back to the Cell case and KK comments about how IBM were pissed off by his choice to go with 8 SPU and thus having a chip bigger than 190mm^2.

If late Nvidia presentation have truth to them it may have gotten worse.
So you may be back to 2 chips, but using the same Nvidia presentation, designing, implementing 2 different and complex chips could prove quiet expansive.
I won't loop to my dual SoC rant
Seeing Pitcairn at 212mm² and Tahiti at 365mm² at the beginning of the 28nm life cycle, it won't be a problem at all to get 300+mm² dies with very high yields in a year from now. And a single chip solution simplifies later shrinks tremendeously (smaller individual chips may be prone to pad limitations). Even if the production cost for the single die may be a bit higher (which probably won't be the case for a mature process as it will be smaller than the sum of the individual chips, one saves the interface between them and the latency is lower which helps performance), but you save something on the PCB and cooling solution too, which helps to offset this.
Would that same logic still apply if the GPGPU in the APU is being used for it's computing power & not as a GPU?
Yes. Whatever you'd run on GPGPU in the APU, you could run on a larger discrete GPU. It'll be finished sooner and then you'd return to rendering graphics. Potentially close workload between GPU and CPU in an APU could execute faster, but you have the lack of versatility when the devs want pure graphics work.
True. And if the need for a fixed allocation of resources to a certain compute task arises, one could do that too, as compute tasks have their independent queues (that's what GCN's ACEs are for).
 
I didn't get that impression from him :?:
Starting with fehu:
fehu said:
From what I understand, if you are not in need to reduce heat or up frequency, new processes are to expensive for 1-2 years from introduction, and going forward it looks even worst
almighty said:
How can getting more chips per wafer make it too expensive and not worth while?
anexhume said:
Yield is lower to start and fab house has to recoup cost of developing process plus higher demand with less volume means higher pricing.
Hence consoles don't switch immediately, instead waiting until the price advantage is there. Which is obvious really - if there was a price advantage, why wouldn't the console companies use it? ;)
 
Starting with fehu:


Hence consoles don't switch immediately, instead waiting until the price advantage is there. Which is obvious really - if there was a price advantage, why wouldn't the console companies use it? ;)

But is there any records or details to back up the claims that it takes 1-2 years to recoup the costs?

For me that's a very long time and says to me that they move onto a newer smaller process without having paid for the previous one.
 
But is there any records or details to back up the claims that it takes 1-2 years to recoup the costs?
No-one's said that. It's said that the option of the new node is too expensive for 1-2 years for consoles to consider, and it's explained that that's because of: 1) lower yields; 2) a need to recoup costs; 3) higher demand pushing up prices. Thus a switch to a new node will start with premium parts, taking a hit to the yields to produce smaller, lower power draw (or larger) chips which are sold at a premium. Consoles and other CE devices can only switch to smaller processes when they have become commoditised.
 
For consoles 1-2 years is probably around right, but it is a bit of an exaggeration as far as any device in general is concerned. It's been almost a year since the first consumer 28nm product - and what's using the node currently? GPU's... that's still pretty much it. Now they're only on the latest node because of performance/watt, or since wattage is more or less the performance limiter in the high end space, just performance alone. With a console performance is static, so cost is by far paramount over everything else. Since smaller chips reduce cooling and case sizes as well as power supply capacity and main board complexity (wrt power distribution), then the main reason for reducing wattage is also a cost one. Reliability and quicker production in the way of more chips per wafer (obviously only once yields are good enough) would be the only other reasons I can think of.

There is no big rush to get to a new node for more performance with consoles, only cost. Hence, they wait until the new nodes are cost effective. I can still see them switching to 20nm a little earlier than usual, however. That is, if they go fairly cutting edge with a 250-350mm^2+ SOC. Since 20nm is due in late 2013-early 2014, they may feel the pressure to transition within a year of its introduction (maybe before holidays 2014) - such a quick transition would probably never be repeated throughout the life of the console.
 
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250mm^2 is not big chip, it's a bit below medium size. The SOCs going into next gen systems will most likely dwarf a 250mm^2 chip.

It's only big by Nintendo standards.

I think 300mm will be the upper limit.

A chip around 450mm will generate around 100 dies per wafer (300mm). Assuming perfect yields your cost for the silicon (prior to testing and packaging) is around 50-$80 per chip. With a chip that big, it's not unlikely that yields would be below 50%, so double the cost right there.

The added problem is that unlike GPU manufactures, MS/Sony can't resell the faulty chips as lower level products so you really have to have good yields from the get go (or be willing to eat the losses).

I think any chip that's more than $150 (final cost after test and packaging) is too expensive.

The original estimates for the 360's BOM by isupply had around $140 for the GPU, $100 for the CPU, $50 for the memory. I don't think they'll go down that route again.
 
For consoles 1-2 years is probably around right, but it is a bit of an exaggeration as far as any device in general is concerned. It's been almost a year since the first consumer 28nm product - and what's using the node currently? GPU's... that's still pretty much it. Now they're only on the latest node because of performance/watt, or since wattage is more or less the performance limiter in the high end space, just performance alone. With a console performance is static, so cost is by far paramount over everything else. Since smaller chips reduce cooling and case sizes as well as power supply capacity and main board complexity (wrt power distribution), then the main reason for reducing wattage is also a cost one. Reliability and quicker production in the way of more chips per wafer (obviously only once yields are good enough) would be the only other reasons I can think of.

There is no big rush to get to a new node for more performance with consoles, only cost. Hence, they wait until the new nodes are cost effective. I can still see them switching to 20nm a little earlier than usual, however. That is, if they go fairly cutting edge with a 250-350mm^2+ SOC. Since it is due in late 2013-early 2014, they may feel the pressure to transition within a year of its introduction (maybe before holidays 2014) - which would probably never be repeated throughout the life of the console.

Pretty much all the cell phones are using 28nm. Earlier in the year Qualcomm indicated supply issues with the S4 because TSMC didn't have enough wafers.


It actually wouldn't surprise me if the 20nm was fairly short lived. Both TSMC and GF are going for a finfet process at 14/16nm for 2014. I know they've slipped always when they promised, but I think they're being really aggressive and investing a lot because they have to close the gap with Intel.

If MS and Sony can break even on the sales of the new consoles, they can probably ride out 2014 at launch price and release a shrink/slim version on a 14/16nm in late 2015 (process should be mature by then).
 
Pretty much all the cell phones are using 28nm. Earlier in the year Qualcomm indicated supply issues with the S4 because TSMC didn't have enough wafers.


It actually wouldn't surprise me if the 20nm was fairly short lived. Both TSMC and GF are going for a finfet process at 14/16nm for 2014. I know they've slipped always when they promised, but I think they're being really aggressive and investing a lot because they have to close the gap with Intel.

If MS and Sony can break even on the sales of the new consoles, they can probably ride out 2014 at launch price and release a shrink/slim version on a 14/16nm in late 2015 (process should be mature by then).

Cell phones are using 32 nm not 28
 
Cell phones are using 32 nm not 28

No, check Qualcomm Snapdragon S4. AFAIK all the Snapdragon S4 chips currently in use are build on a 28 nm process at TSMC. Oh, and Qualcomm seems to be doing very good business these days, as they've climbed up to the number 3 spot in the preliminary list of the top 20 semiconductor suppliers for 2012.

EDIT: I don't seem to have all my facts straight. UMC is also manufacturing chip on their 28 nm node for Qualcomm and Qualcomm has signed an agreement with Samsung to manufacture Snapdragon chips on 28 nm in one of Samsung's fabs. In other words, all Snapdragon S4 chips currently on the market are made on 28 nm, but they're not all made at TSMC. Oh, and apparently they are also using Globalfoundries. Geez, Qualcomm must have needed a lot of chips build.
 
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No, check Qualcomm Snapdragon S4. AFAIK all the Snapdragon S4 chips currently in use are build on a 28 nm process at TSMC. Oh, and Qualcomm seems to be doing very good business these days, as they've climbed up to the number 3 spot in the preliminary list of the top 20 semiconductor suppliers for 2012.

EDIT: I don't seem to have all my facts straight. UMC is also manufacturing chip on their 28 nm node for Qualcomm and Qualcomm has signed an agreement with Samsung to manufacture Snapdragon chips on 28 nm in one of Samsung's fabs. In other words, all Snapdragon S4 chips currently on the market are made on 28 nm, but they're not all made at TSMC. Oh, and apparently they are also using Globalfoundries. Geez, Qualcomm must have needed a lot of chips build.

They sure do, and it shows - they actually passed Intel in company market value already.
 
If it would be true that "We know everything about multi-graphics card solutions", why do we have this crappy AFR solutions?
Could it be that for now MSFT through Direct x and Kronos through Open CL never considered that there really was a purpose for multi gpu in the 3d realtime rendering realm?
It may be an false memory, but I remember an eminent member here, Andrew Lauritzen, I hope I'm not wrong, stating that the issue was more related to the API than to really tricky software engineering problem. I'm sure searching the whole forum with those pretty loose criteria (his wording may have been different) is likely to return me nothing (especially as it could be another devs, researchers. Though I read it from a member well within 3d).
Seeing Pitcairn at 212mm² and Tahiti at 365mm² at the beginning of the 28nm life cycle, it won't be a problem at all to get 300+mm² dies with very high yields in a year from now. And a single chip solution simplifies later shrinks tremendeously (smaller individual chips may be prone to pad limitations). Even if the production cost for the single die may be a bit higher (which probably won't be the case for a mature process as it will be smaller than the sum of the individual chips, one saves the interface between them and the latency is lower which helps performance), but you save something on the PCB and cooling solution too, which helps to offset this.
Well if anything Pitcairn is tinier than its predecessors. Tahiti on the other hand bigger.
There was complain actually about the price of those cards (including cap verde).(Actually we don't know how high the yields were and there were shortage which further information could be due to AMD not securing enough wafers, Yields or a blend of both).
But I think it is irrelevant to the quote I gave. There are high yields big chips for sure but it still doesn't discard what KK said.
I know close to nothing about lithography techniques used nowadays, so far ( I asked once) nobody could tell me precisely what is the impact/cost of going with chips bigger than 185mm^2.
Even less if that limitation is still valid.
KK seems to imply that it makes the process more complex, you do more work. it may take longer?
He doesn't speak about yields, I don't think that what he is speaking about is that yield would decrease all of sudden. Those it could be that when you do the second exposure, it is tough to be perfectly align, etc, which would result in a raise in defects per mm^2.
You have to do a second exposure, I don't know how that done, but that indeed seems to imply an extra step, so extra costs by self.
Imho big chip with good yield are irrelevant to his talk.
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THen there are the late Nvidia presentation about raising cost for implementing logic on new process, but may it is PR to explain "things" to investors. I would not discard Nvidia comment without a serious counter argument ( it won't come from a forum, it would take another company pointing the fact that cost are not raising,but are either constant or decreasing).

EDIT
I found some of the slides presented by Nvidia, google is impressive :LOL: I did not expect it to return anything significant with the crap I fed it.
link
There are also a couple slides from other sources (not Nvidia) in that article. Imo it doesn't look that good.
The last part of the article seems to imply that industry should give up on big die and try hard to make stacking happen (though it is easier said than done).
Looking at both Nvidia and TSMC slides one may wonder if actually moving from 28nm to 22nm will be a sane option before years (not the couple that we usually had in the console realm, half node shrinks are already a thing of the past).
 
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THen there are the late Nvidia presentation about raising cost for implementing logic on new process, but may it is PR to explain "things" to investors. I would not discard Nvidia comment without a serious counter argument ( it won't come from a forum, it would take another company pointing the fact that cost are not raising,but are either constant or decreasing).

No, they're right. It is getting more and more expensive to go to smaller geometries. Several years ago I worked for a startup that taped out a 65nm (fairly large) chip for the price of $6-10M, at 28nm I believe that tapeout would be around 3-4X that amount. At 20nm, it will be even more expensive. I'm not sure how small companies will be able to compete in the future. It's just too much of an investment. Going to 450mm wafers should help long term costs, but the initial cost will be more.

But, the cost of silicon isn't the only reason for going to a smaller node. Power consumption should go down (and performance can increase). In a console system, reducing power consumption should allow for an overall smaller BOM thanks to smaller power supplies, cooling system, smaller form factor. Also, the smaller geometry may allow for more chips (like Wifi/Ethernet) to be integrated into the SOC, not just the CPU/GPU. Sure those aren't big things, but when you sell millions of units that stuff adds up.
 
No, they're right. It is getting more and more expensive to go to smaller geometries. Several years ago I worked for a startup that taped out a 65nm (fairly large) chip for the price of $6-10M, at 28nm I believe that tapeout would be around 3-4X that amount. At 20nm, it will be even more expensive. I'm not sure how small companies will be able to compete in the future. It's just too much of an investment. Going to 450mm wafers should help long term costs, but the initial cost will be more.

But, the cost of silicon isn't the only reason for going to a smaller node. Power consumption should go down (and performance can increase). In a console system, reducing power consumption should allow for an overall smaller BOM thanks to smaller power supplies, cooling system, smaller form factor. Also, the smaller geometry may allow for more chips (like Wifi/Ethernet) to be integrated into the SOC, not just the CPU/GPU. Sure those aren't big things, but when you sell millions of units that stuff adds up.
By any chance do you know what KK is exactly speaking about?
I'm ignorant of the whole process and I don't really know what he is speaking about (seems like I'm not alone I haven't found a single comment really explaining what it is about).

Wrt to moving to smaller node it still has advantages, you pointed that out really well, but mixing everything together, the raising costs (and thus from consoles manufacturers pov shrinking is less sexy, is to be pursued less aggressively), it seems to me that the "technicality" KK was speaking about (and vouch against but we are now at different point in the technology curve) would be even more relevant now.
 
I think 300mm will be the upper limit.

A chip around 450mm will generate around 100 dies per wafer (300mm). Assuming perfect yields your cost for the silicon (prior to testing and packaging) is around 50-$80 per chip. With a chip that big, it's not unlikely that yields would be below 50%, so double the cost right there.

The added problem is that unlike GPU manufactures, MS/Sony can't resell the faulty chips as lower level products so you really have to have good yields from the get go (or be willing to eat the losses).

I think any chip that's more than $150 (final cost after test and packaging) is too expensive.

The original estimates for the 360's BOM by isupply had around $140 for the GPU, $100 for the CPU, $50 for the memory. I don't think they'll go down that route again.

There's several different factors that affect yield though. They could have a large part that has inherently lower yields per wafer. They could have an aggressive frequency plan that bins a lot of them to the trash. They could have a part that has lower yield because of odd geometries or some design guidelines that weren't followed. Each of these would improve in different ways as processes matured and die shrinks came (die shrink is an automatic opportunity to fix geometry problems, for instance).

Which of those sacrifices would they be willing to accept? Especially since launch availability affects sales too. I would think they'd go for a smaller part that yields poor because of frequency requirements because a die shrink would almost assuredly fix that. A big part on the previous process would still be a (comparatively) big part on the smaller process. Seems that's better for long term, but I don't know.
 
Could it be that for now MSFT through Direct x and Kronos through Open CL never considered that there really was a purpose for multi gpu in the 3d realtime rendering realm?
It may be an false memory, but I remember an eminent member here, Andrew Lauritzen, I hope I'm not wrong, stating that the issue was more related to the API than to really tricky software engineering problem. I'm sure searching the whole forum with those pretty loose criteria (his wording may have been different) is likely to return me nothing (especially as it could be another devs, researchers. Though I read it from a member well within 3d).

If what I remember is accurate, the initial problem was the way in which the APIs enumerate multiple devices; they didn't. Therefore it was up to the driver to shuffle the workload around. The device enumeration has since been resolved.

Now you're left with the premise of "exactly how do we split the work?" which is the rather difficult and tricky software engineering problem for IMRs (Immediate Mode Renderers). In the initial days this was simplier to use the even-odd splitting since the rendering was not as advanced (no MRTs for instance). Now with MRTs and a metric ton of other complex algorithms its not so straight forward.
 
If there are still doubts that Sweetvar26 had legitimate leaks, this should lay them to rest.

http://www.afterdawn.com/software/version_history.cfm/hwinfo64 said:
Enhanced sensor monitoring on ASRock Z77, Z75, H77, B75, Q77, H71M and A75 series.
Minor bugfixes and improvements.
Driver management tool removed from package. Functionality moved into Configure section.
History file removed from package. Available online in the News section.
Help file replaced with on-line help (forum).
Embedded all supplemental files (DAT, drivers) into the main EXE file.
Reduced package content to 2 files only (EXE, INI).
Added reporting of GPU VDDC for later AMD GPUs.
Enhanced sensor monitoring on Gigabyte F2A85 series.
Added preliminary support of Nuvoton NCT6791D sensor.
Added AMD Sun, Neptune, Ibiza, Cozumel, Kauai, Hainan, Curacao, Aruba, Richland Devastator/Scrapper, Thebe, Kryptos, Samara, Pennar.
Added reporting of SATA AHCI/RAID controller and per-port information under PCI host device.
Fixed reporting of current memory clock on AMD Trinity.
Enhanced reporting of current memory parameters for Haswell.
Enhanced sensor monitoring on ASRock Z77 OC Formula.
Added support of Intel Wellsburg.
Added nVidia Quadro K2000, K2000D, K600, NVS 510, K5000, VGX K1, VGX K2.
 
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