I don't know, apparently der8auer doesn't either. It's likely that because it was an engineering sample and possibly not representative of the final product (as Ian Cutress alluded to) that it provided incorrect information regarding Threadripper.
Memory and peripheral I/O wiring for TR/Epyc(?)
Beautiful.
So Threadrippers are just Epyc fails? :|
Anarchist4000
Veteran
More of a "glass half full/empty" thing. So much for the Epyc pencil mods!
Possibly, although as a slave device there would be classes of issues where Vega would defer to a CPU.
What some of the exception or fault handling would do if data within an encrypted VM was associated with an error that propagated up to the hypervisor is uncertain. It would seemingly constrain some of the tools used to allow systems to manage failures or log data, unless those became a vector for leaking data.
Involving the secure enclave in link errors and calling interrupt/exception code might itself become a vector via bus-glitching or some kind of malicious remote node.
That would scale horribly on just four mem channels.
I wonder how much more would a X399 motherboard cost with fully wired SR3 socket.
Another possibility claimed to have been disclosed in the following is that the other dies are mechanical placeholders.
http://www.pcworld.com/article/3211...en-threadripper-has-two-mysterious-chips.html
Not much distinguishing detail from a distance and under a solder layer to discern if they are.
http://www.pcworld.com/article/3211...en-threadripper-has-two-mysterious-chips.html
Not much distinguishing detail from a distance and under a solder layer to discern if they are.
hoom
Veteran
Probably depends on how sales go/how hard Intel fights.
Jawed
Legend
That's Gubbi's point.
As far as I can tell the sockets for EPYC and Threadripper are only marginally different. So wiring up and fitting the memory on a consumer mobo is the real question, I suppose. You end up with a server mobo and server processor. So why even make consumer 32 core Threadripper and mobo...
As far as I can tell the sockets for EPYC and Threadripper are only marginally different. So wiring up and fitting the memory on a consumer mobo is the real question, I suppose. You end up with a server mobo and server processor. So why even make consumer 32 core Threadripper and mobo...
He is quite sure that the information pertained therein still is legit. Maybe they want to do yet another double blind test. Like - can you feel the difference in L3 latency...
Anarchist4000
Veteran
Might make sense if the pins were re-purposed for power delivery. Save costs from 4 fewer memory channels, but leave open the possibility of other accelerators with integrated memory: FPGAs, DSPs, GPUs, stacked DRAM, etc. That would follow their heterogeneous capabilities when Epyc with 128 PCIE lanes was overkill. Threadripper ITX platform, with a dozen USB3.1 ports, Thunderbolt, dual 10GbE networks, etc that wouldn't be excessive at all.
https://www.amd.com/Documents/AMD-Product-Master.pdf
via https://www.planet3dnow.de/cms/3314...p-b1-somit-kein-teildeaktivierter-epyc-zp-b2/
6 Threadripper models, 1900(X), 1920(X), 1950(X).
TDP different between non-X and X-models
All of them use Zeppelin B1-stepping while Epyc uses B2-stepping
via https://www.planet3dnow.de/cms/3314...p-b1-somit-kein-teildeaktivierter-epyc-zp-b2/
6 Threadripper models, 1900(X), 1920(X), 1950(X).
TDP different between non-X and X-models
All of them use Zeppelin B1-stepping while Epyc uses B2-stepping
It's close to an i5-2500K, so probably close to that too:
http://www.hardware.fr/articles/966-4/performances-applicatives.html
Interesting, TR parts will have more than twice the cache of R7 CPUs: https://videocardz.com/newz/amd-confirms-tdp-and-cache-of-ryzen-threadripper
How is that possible when using two Zeppelin dies? 2x would put them at 32mb, 40mb is a 25% increase over that.
Edit: They must be counting L2 + L3 for that to make sense. 32mb L3 + 8/6 mb L2
How is that possible when using two Zeppelin dies? 2x would put them at 32mb, 40mb is a 25% increase over that.
Edit: They must be counting L2 + L3 for that to make sense. 32mb L3 + 8/6 mb L2
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