AMD: Volcanic Islands R1100/1200 (8***/9*** series) Speculation/ Rumour Thread

SSAA is enough, why do you want SGSSAA ( the simil SSAA made by Nvidia but who is not Supersampling AA ? )

SGSSAA = Sparse Grid SuperSample AA
just "SSAA" can refer to SGSSAA, RGSSAA or OGSSAA (from best to worst)
 
SGSSAA = Sparse Grid SuperSample AA
just "SSAA" can refer to SGSSAA, RGSSAA or OGSSAA (from best to worst)

If you do 4x, there'll be hardly any difference between sparse grid and rotated grid I think, or none at all (grid configured to be the same as rotated).
 
So I guess people hoping for a L2 cache increase are disappointed (just the increase due to more MC channels, no additional doubling).
 
So I guess people hoping for a L2 cache increase are disappointed (just the increase due to more MC channels, no additional doubling).

I think, they will not push more L2 size of what it is needed,.. look good for me. question of balance. 1Mb read and write..

@Kaotik, you are right my bad..
 
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Doubling the number of geometric blocks and led to an increase in units RBE, which positively affected the rate of filling of pixels (pixel fillrate). Important role in this was played by the parameter optimization cache in the second level L2: increased its volume (from 768 KB to 1 MB AMD Radeon R9 290X) and internal bandwidth (with 700 MB / s to 1Tb / s AMD Radeon R9 290X).

Hawaii GPU has more L2 than Tahiti? :rolleyes:
 
Hawaii GPU has more L2 than Tahiti? :rolleyes:

16x 64kb allocation....

Personally im surprised by the change vs GCN 1.0 .. nearly all triangle and geometry processors, rasterize have been moved inside the SM, only the ACE£s ands command are left outside. Something really similar to what you can see in Kepler or Fermi .. Alll the rest of the architecture is a follow up of this.. ( L2 cache, ROPS and Pixell fillrate )..

This arch in 20nm...( for the next serie ) will be a killer.. imagine what you can do with that in 20nm.

now i still wait about the DP rate...
 
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16x 64kb allocation....

Personally im surprised by the change vs GCN 1.0 .. nearly all triangle and geometry processors, rasterize have been moved inside the SM, only the ACE£s ands command are left outside. Something really similar to what you can see in Kepler or Fermi .. Alll the rest of the architecture is a follow up of this.. ( L2 cache, ROPS and Pixell fillrate )..

This arch in 20nm...( for the next serie ) will be a killer.. imagine what you can do with that in 20nm.

now i still wait about the DP rate...

Makes me think hawaii was planned on a smaller 20nm die originally and once they caught wind of 20nm delays or titan or who knows what, they decided they could afford a larger 28nm die with the same layout.
 
Personally im surprised by the change vs GCN 1.0 .. nearly all triangle and geometry processors, rasterize have been moved inside the SM, only the ACE£s ands command are left outside.
SM being an Nvidia term, the shader engines distribute some things like registers and scheduling logic a little differently with the CU setup.
Some of the high level similarities seem indicate someone reached a more optimum design decision earlier.

That being said, some of the subdivisions in GCN appear to have already existed in the first GCN chips. The term shader engine, and how it groups CUs, was mentioned earlier in this thread. Tahiti has four.

The diagram is pretty high-level and not in the same style as the ones used for Tahiti, so we are left to wonder how much is an architectural versus stylistic change.
The earlier diagrams did show some kind of subdivision of the ROPs, CUs, and the two geometry and raster units. Some of the lines drawn in the 7970 diagram could look like the new diagram, if expanded in the same manner.
What Hawaii could be doing is doubling the pixel pipe and primitive pipes and dispensing with some of the interconnection that was needed for Tahiti when there were more shader engines than ROP partitions or geometry pipes.

The GDS is in a different position in the diagram, which might mean something about its use in the new front end and work distribution process.
Given the number of elements that want to use it, it would be nice if it got more love than just more purple pixels in the diagram.
 
if each shader engine is 11 CUs, how would they cut the 290 from that? It will be 4/11th of a shader engine disabled? Or maybe 1 cu from each disabled?
 
My mistake for trying to make sense of that whole interchange.

edit:
On reflection, that may have come out more snarky than self-deprecating.

Thank you for the clarification.
 
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