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[0029] Turning now to FIG. 2, FIG. 2 illustrates a method 50 of outputting a video stream. At 52, method 50 includes retrieving from memory a first plane of display data having a first set of display parameters. It can be appreciated that "plane" as used herein refers to a plane (e.g., layer) of a 2D memory buffer, and thus is distinct from a plane in the traditional sense with respect to a plane of a 2D image. Planes may correspond to (e.g., be sourced by) application-generated display data or system-generated display data, resulting from, for example, frame-buffer(s) produced by the graphics core and/or other system components. Further, planes may be associated with various sources such as main sources, HUD sources, etc. and thus, the first plane may be any such suitable plane.
[0030] For example, the first plane may be an application main plane comprising an application-generated primary-application display surface for displaying primary application content (e.g., main screen of a driving game). As another example, the first plane may be a system main plane comprising a system-generated primary-system display surface for a computing system (e.g., a window displaying system messages).
[0031] The first plane has an associated first set of display parameters. Such display parameters indicate how display data of the plane is to be displayed. For example, display parameters could include resolution, color space, gamma value, etc. as described in more detail hereafter.
[0032] Further, the first plane may be retrieved in any suitable manner, such as by direct memory access (DMA). As an example, the DMA may retrieve front buffer contents from a main memory. As such, a system-on-a-chip (SoC) may be designed to deliver a favorable latency response to display DMA read and write requests. The memory requests may be issued over a dedicated memory management unit (MMU), or they may be interleaved over a port that is shared with the System GPU block requesters. The overhead of the GPU and SoC memory controllers may then be taken into account in the latency calculations in order to design a suitable amount of DMA read buffering and related latency hiding mechanisms. Display DMA requests may be address-based to main memory. All cacheable writes intended for the front buffers may optionally be flushed, either via use of streaming writes or via explicit cache flush instructions.
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[0038] The video scaler may further provide for dynamic resolution adjustment based on system loading for fill limited applications. As such, the resampler may be configured to support arbitrary scaling factors, so as to yield minimal artifacts when dynamically changing scaling factors. Further, resampling may be independent on each of the sources of the planes. In such a case, a high quality 2D filter such as a high quality non-separable, spatially adaptive 2D filter may be desirable for a main plane, whereas non-adaptive, separable filters may be used for HUDs.
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[0050] By performing such post-processing on a per-plane basis, attributes of the sources (e.g. color space, size, location, etc.) can change on a frame by frame basis and therefore can be appropriately buffered to prevent bleeding/coherency/tearing issues. Thus, all display planes may be updated coherently.
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[0058] At 76, method 50 includes outputting the blended display data. In some embodiments, the blended display data may be output to a video encoder. However, in some embodiments, content that is formatted and composited for output may be written back into memory for subsequent use, including possible video compression. The source may be taken from any blending stage, for example, to include or exclude system planes. Alternatively, for fuller flexibility, a separate set of blenders may be added. Such outputting to memory also provides a debug path for the display pipeline.
Read more: http://www.faqs.org/patents/app/20110304713#ixzz2KeFveMEu
