AMD: R9xx Speculation

the r300 launched before dx 9 and offered extremely playable framerates on dx 9 games which no first gen dx card has managed to accomplish. It also brought playable fsaa to new games instead of just older games.


So what can cayman do ?

Current cards already play dx 11 games at playable framerates. Perhaps Eyefinity at high fsaa amounts in a single gpu? I don't really know if thats R300 level tho.

The problem with the current dx 11 games is that minimun frame rates are far from the medium fps.
 
Virtually all current games are GPU limited at high resolution and AF/AA so Cayman can allow for higher resolutions with higher AF and AA and that will be great, but it's not going to be the mind-blowing change that the 9700 Pro was where you could finally play games with both at playable framerates for the first time.
 
The BGA pattern is very similar to the Cypress' contact array. Pin-compatible? Probably not exactly, if the TDP is so sky-high.
 
I think it said off-die buffering, which could just mean writing intermediate results to memory. That doesn't require a special chip.
 
IF AMD promotes Cayman as "new R300", they must be smokin' really good stuff :)
First of all, its Fudo, take whatever he says with a train of salt ;)

Still I'm pretty sure Cayman will be pretty good chip, and if GTX580 wont be something much better than GF100b, we can expect another year of AMD domination.
 
I think it said off-die buffering, which could just mean writing intermediate results to memory. That doesn't require a special chip.
Yes the curious thing is that this description of off-die buffering was associated specifically with tessellation. It seems that off-die buffering of tessellation data is an "improvement" on keeping that data in the SIMDs (seemingly in LDS?). Maybe that's because it's easier to share it across the chip?

Can't say I like the sound of this, though - it might be an improvement, but ugh, cached like in Fermi seems preferable. And 2x the geometry performance, if true, sounds like no real improvement.
 
Yes the curious thing is that this description of off-die buffering was associated specifically with tessellation. It seems that off-die buffering of tessellation data is an "improvement" on keeping that data in the SIMDs (seemingly in LDS?). Maybe that's because it's easier to share it across the chip?

Could it be about capacity?

Can't say I like the sound of this, though - it might be an improvement, but ugh, cached like in Fermi seems preferable. And 2x the geometry performance, if true, sounds like no real improvement.

How is 2× not an improvement? Especially since that's probably 2 × setup rate, on top of improvements found in Barts.
 
Interesting these slides say 2GB frame buffer whereas previous ones said 1GB. Any chance we're seeing the first major consumer level implementation of 2Gb GDDR5 modules here?
 
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