AMD: R9xx Speculation

A ~190mm2 chip *might* be too small for a 256 bit bus. I remember rv770 being pad limited for a 256 bit bus @260mm2. Not to mention that the memory bus is likely to run much faster than rv770.

I reckon the factors in making RV770 pad-limited (any other ideas?):
  • power - don't feel like working out how many I/O pads there are, but the remainder should be power related
  • complexity of GDDR5 - requires more pads than GDDR4 (RV670 is 192mm² 256-bit GDDR4)
  • GDDR5 clocks - presumably higher clocks require more area
  • sideport - this is a funny one. It takes something like 5.6mm of perimeter. But there is no need for it to take so much perimeter, as it should be stackable (see how PCI Express is stacked on GT215 - 2 lines of pads along the perimeter instead of a single line). Note also that it's theoretically PCI Express, electrically, but at much lower power. The area consumed by the sideport I/O in RV770 is about 38% of the PCI Express I/O. Which implies to me that stacking should be easier
In theory we're expecting sideport to make a return in this next family, but that might be a feature of the biggest chip only, on the basis that it's only for a single card with dual GPUs.
Against all that is the under bump routing layer patent application. The gist of that is the ability to deliver power to parts of the chip without being limited by the density of solder balls. This should mean it's possible to deliver power to the I/O areas of the chip without cluttering the I/O solder balls with power balls.

http://v3.espacenet.com/publication...T=D&date=20090205&CC=US&NR=2009032941A1&KC=A1

I presume this reduces the "pad limitation" of high bandwidth GDDR5. Having said that, it looks old enough that it should have been part of RV770.

Alternatively this is not about pad limitation, but merely changing the distribution of power solder balls across the surface of the chip (since solder balls are current limited in aggregate). So the solder ball count would remain unchanged, and there'd be no effect on overall pad limit. I don't know how much give and take there is, e.g. some solder balls might have spare current capability before the application of this document's technique.

I wouldn't be surprised if Barts looks the same size as RV770 on the back of its board.
 
What do you think about an increase in practical textur fill-rate on NI-chips?

The situation now:
rm3daniso.gif

http://techreport.com/articles.x/19242/6

So if AMD is able to reach the same per texel real-time performance as on Juniper, Barts and Cayman may reach the following performance numbers:

Barts XT (64 TMUs @ 900MHz?): ~28,9 GTex/s -> 5870+11%

Cayman XT (96 TMUs @ 900MHz?): ~43,4 GTex/s -> 5870+67%
 
Btw. OBR, who leaked some of the NI's slides, today posted a comment (translated): "Who said, that SPs were changed from 5D to 4D? I wish you weren't disappointed"
 
Btw. OBR, who leaked some of the NI's slides, today posted a comment (translated): "Who said, that SPs were changed from 5D to 4D? I wish you weren't disappointed"

I'm not sure I understand what he's saying here… :???: Is that Googlenglish or a proper translation?
 
I wouldn't be surprised if Barts looks the same size as RV770 on the back of its board.
I remember rumours about pin to pin compatibility with the 5XXX generation chips. If true, then it might not be only the size that is going to be the same at the boards. :)
 
I'm not sure I understand what he's saying here…
He (more or less) comments the optimistic speculations about 4D ALUs, which are expected to boost efficiency quite significantly. If I got his comment, he's hinting, that ALUs are still 5D.
 
Btw. OBR, who leaked some of the NI's slides, today posted a comment (translated): "Who said, that SPs were changed from 5D to 4D? I wish you weren't disappointed"

If the SP-s are 5D than the vantage scores (if they are true ;)) with 800 SP-s and 960 SP-s are quite impressive against 1440 and 1600. :rolleyes:
 
May I, then?

Caicos: Low-end, err… sorry, "Value"
Turks: Mainstream
Barts: Performance
Cayman: Enthusiast
Antilles: "I've got the biggest!"
 
Thanks!

Alexko > Universal......


Ooch, really? :LOL::LOL::LOL: You have to be very very thankful that NVidia is sleeping deeply. Otherwise Cayman would be mainstream. :LOL: In reality it is, but AMD is confusing all of us and using the situation in the way it likes....

Stop it, please.
 
Ooch, really? :LOL::LOL::LOL: You have to be very very thankful that NVidia is sleeping deeply. Otherwise Cayman would be mainstream. :LOL: In reality it is, but AMD is confusing all of us and using the situation in the way it likes....

Stop it, please.

I have no idea what you're on about.

You've already seen NV's answer to N.I., where you impressed?
 
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