NVIDIA Fermi: Architecture discussion

Does D3D11 compliance require hardware support, sorry for the dumb question Rys. :p
If it's a software pipe there won't be zero transistors dedicated to tesselation, it just won't be a block.

As for FMA, in graphics mode the driver will issue one for every existing MADD, which is problematic. The alternative is running it in two clocks.

No MUL will be issued on the SFU.
 
I don't know if they're separate like that, but one GT200 diagram at the Tesla Editor Day clearly indicated separate INT units and then an engineer told me outright that was only marketing when I asked. Maybe it's the same this time around, or maybe it isn't.
Seems pretty unlikely to me they are really fully separate, looks like too many wasted transistors to me. Even doing something like fp mul + int add at the same time (which you could argue all those mad-capable gpu cores can almost do without additional transistors) would require the core to be able to fetch 4 arguments and write 2, and that might be problematic.
 
@1.5GHz/6GHz, but that may only be the current ones.

Target of 750, I doubt they will be able to do it.

2:1 ratio, the targets are 1.5TF SP, 768GF DP, but again with the caveat of clocks willing. I have reason to believe they won't be unless you are in the press.
Source + reason? ATI? If you're certain of the numbers, please print them :D
 
ok so there is still a dual issue but now you can do two madd's? or 2 mul's or two add's as needed?

edit nm, just read the article with about the mul!
 
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i really enjoyed day 1 of the GTC. i will have some images later of all sides of the new Fermi (including the big chip).

Jensen made it clear that "Tesla" was never the name for GT 200 architecture and Brian Burke told me that Fermi is the first name for GPU architecture named after a scientist.

i will get more clarification tomorrow when i do an interview. Anything you want me to ask?
 
All memories the chip talks to, from registers up, are ECC protected (potentially, nobody ships ECC GDDR5, and I think the chip will address 'PC' DDR3 for that in the end). Not sure what scheme or penalty.
Hmm using ddr3 would impose a huge bandwidth penalty.
I wonder, couldn't you use just 3 normal (32bit) gddr5 chips per memory channel instead of 2 and then only use 64bit + 8bit for ECC? Sure that would be waste of memory but at the price those tesla cards are likely going to be sold it should be a non-issue (and the more consumer oriented cards certainly won't do that).
 
We need another 'poll' thread as to NV's next code name, my money is on "Gauss" :)

According to Brian Burke, Firmi is Nvidia's first scientist's name used as a code name for their new GPU architecture

He (and Jensen) made it very clear that Tesla is not the name of the GT 200 chip's architecture
 
Source + reason? ATI? If you're certain of the numbers, please print them :D

Why do you think I get my info from ATI? Because Fudo wrote it up and Theo parroted it back?

All this said, no, I am not going to 'prove' my numbers. Yes I am certain of them, I wouldn't have printed them if I wasn't. I have an article on this coming, but I haven't been able to finish it yet.

One of the biggest problems is that NV itself doesn't have enough working silicon to characterize the #(*$&ing parts.

The target is 750 +/- a bit. Will they get there? I doubt it, G200 missed targets by 10+% and 7 months, and this one is more rushed, plus has about 5 very critical risk areas.

They aren't giving out specs because they don't have a clue what they can make yet.

-Charlie
 
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