That's not how it was! IF the evergreen line would have been delayed, there would have been a need/use for 4890X2. Evergreen was not delayed hence no need of 4890X2.
AMD: R8xx Speculation
- Thread starter Shtal
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That's not how it was! IF the evergreen line would have been delayed, there would have been a need/use for 4890X2. Evergreen was not delayed hence no need of 4890X2.
But is dropping of X2 moniker for Evergreen family a sign of a bit more than usual CrossFire on board?
I know that from marketing POV dropping X2 is better, because consumer will understand market position of a product, whenever with HD4870X2 faster than HD4890 this wasn't so clear to Joe the Average.
On the other hand this hasn't stopped AMD from doing this for HD3800 and HD4800 series, so why now
I know that from marketing POV dropping X2 is better, because consumer will understand market position of a product, whenever with HD4870X2 faster than HD4890 this wasn't so clear to Joe the Average.
On the other hand this hasn't stopped AMD from doing this for HD3800 and HD4800 series, so why now
But is dropping of X2 moniker for Evergreen family a sign of a bit more than usual CrossFire on board?
I know that from marketing POV dropping X2 is better, because consumer will understand market position of a product, whenever with HD4870X2 faster than HD4890 this wasn't so clear to Joe the Average.
On the other hand this hasn't stopped AMD from doing this for HD3800 and HD4800 series, so why now
ATi will probably switch to the 59xx moniker because Nvidia got away from the gx2 nomenclature as well with the GTX 295.
"Higher number = better performance" is better naming convention from a consumer perspective.
I think degustator´s explanation that it will be slower than 2 5870 in crossfire is better. It´s just not 5870x2, as 4870x2 was 2 4870´s.
So AMD is releasing a slower card than originally planned because of lack of competition from nvidia? I´m disappointed (not because of AMD´s decision, but because market is unbalanced and that makes me, as a consumer, buy a worse product). Unless it´s not AFR.
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My point was ATi is following NV's example with the name change. I made no comment WRT specific performance, only that the dual-chip card should feature higher performance than any single-chip card in the same product family.
Jawed
Legend
According to this slide:
http://www.hardocp.com/image.html?i...lRCV1MxWXhXblJsUjBaVVRWWkdORlpYZUZkVmJGcEdWMn
the number of threads in flight in RV870 is no greater than RV770, despite the former having twice the SIMDs.
I'm not sure I believe that.
Jawed
http://www.hardocp.com/image.html?i...lRCV1MxWXhXblJsUjBaVVRWWkdORlpYZUZkVmJGcEdWMn
the number of threads in flight in RV870 is no greater than RV770, despite the former having twice the SIMDs.
I'm not sure I believe that.
Jawed
Jawed
Legend
The number being quoted is per GPU as far as I can tell.
If it turns out that this number is unchanged from RV770 then that says there's a blockage in the architecture of the scheduler (implying that the scheduler is shared by all SIMDs).
Or this limited capability might actually be an artefact of the deletion of SPI, since SPI is designed to allocate registers and setup the state of each thread before shader execution commences. Though I can't really see how that would limit capability, per se.
Bit of a puzzler.
Jawed
If it turns out that this number is unchanged from RV770 then that says there's a blockage in the architecture of the scheduler (implying that the scheduler is shared by all SIMDs).
Or this limited capability might actually be an artefact of the deletion of SPI, since SPI is designed to allocate registers and setup the state of each thread before shader execution commences. Though I can't really see how that would limit capability, per se.
Bit of a puzzler.
Jawed
Silent_Buddha
Legend
Something interesting to think about.
IF AMD is using 59xx for the x2 cards (still have my doubts) but the fact that there's 2 entries for it could mean.
5970 = 5870x2
5950 = 5850x2
Regards,
SB
IF AMD is using 59xx for the x2 cards (still have my doubts) but the fact that there's 2 entries for it could mean.
5970 = 5870x2
5950 = 5850x2
Regards,
SB
I'd imagine this 32K thread count used by AMD means 512 64-pixel batches where pixel=thread?
Perhaps there was no significant gain to having 1024, or there is a trend of increasing complexity of shaders that is putting pressure on having higher register counts allocated per wavefront.
Perhaps there was no significant gain to having 1024, or there is a trend of increasing complexity of shaders that is putting pressure on having higher register counts allocated per wavefront.
AMD's "cores" aren't even at the level of Nvidia's "cores".
Given how the ALUs are clustered, mapping them to Nvidia's parlance would put them at 320.
Given how the ALUs are clustered, mapping them to Nvidia's parlance would put them at 320.
Leakage is variable, but the cores are scaled according to leakage to 2 versions: The 1.165V and 1.125V version. (I don't say revisions, but versions).
You don't stand a chance for a carrier in their marketing departments with this kind of perception of the matter.
Would it work to say there are two bins for that SKU?
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Jawed
Legend
The register file only has 256 addresses, and a thread can only address 127 of those addresses (ignoring, for a second, the varying number of shared registers, which any thread can access, but which are limited in number to 128). So 512 isn't possible.
I am wondering if some of the performance-scaling shortfalls seen with RV870 in games are a direct result of reduced latency-hiding capability per SIMD. Some of the extra cycles added by having 2x the SIMDs are disappearing as the SIMDs are incapable of handling as much latency. Compounded by L1 halving in size per core and with L2->L1 scaling by 0.
In truth this only materially affects shaders that allocate ~5 or less registers per strand on RV770 (50 threads per SIMD), or ~9 or less on RV870 (25 threads per SIMD), as any higher and the count of threads is limited by register allocation anyway.
What proportion of pixel shaders use 9 vec4 registers or less and have a low ALU:TEX?...
Jawed
Jawed
Legend
I didn't notice that, where does it say that? That means that T cannot issue FMA, only MAD, I guess.
Jawed
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