AMD: R8xx Speculation

How soon will Nvidia respond with GT300 to upcoming ATI-RV870 lineup GPUs

  • Within 1 or 2 weeks

    Votes: 1 0.6%
  • Within a month

    Votes: 5 3.2%
  • Within couple months

    Votes: 28 18.1%
  • Very late this year

    Votes: 52 33.5%
  • Not until next year

    Votes: 69 44.5%

  • Total voters
    155
  • Poll closed .
cp09.JPG
 
It can always surprise me, when a person, who can draw such a nice diagram, is unable to remove a logo and use correct colours...
 
All those gotchas not withstanding, I blew up the image and I saw these unique things (not in rv7xx),

-Parallel DMA engine
-Memory Read/Write cache
-Stream output reduction buffers
-Video controller
-1 less display controller
-no sideport
-no uvd
-Programmable tessellator cache
-Something that looks like Isaard controller. I have no idea what exactly it is?
 
Rumour-ish:
• ATI Eyefinity technology with support for up to three displays

Oh, so 3 independent display controllers? Would be very nice.
Every radeon (except the very first one, r100, so only since rv100) had two display controllers. (And it's a very similar story on the green side, every card since GeForce 2 MX / GeForce 4 (not GeForce 3) had two display controllers.)
That's 8 years now we've been stuck with 2 display controllers (ok there was an even longer time graphic cards only had 1...)
 
Ok, lets play along and say its real. Did the rv770 have so many different caches? That digram says it has L2 cache, L1 texture cache, z stencile cache, and color cache. Does that sound right?

Whenever I read discussions on the different caches on the rv770 I always got the impression they were all read only(true?). Would all these caches still be read only, or is there something in there that says OMG this is totally BS for a gpu?
 
There's nothing out of the ordinary. But considering this (rv8xx) is supposed to be a radical change, it seems downright tepid.
 
Ok, lets play along and say its real. Did the rv770 have so many different caches? That digram says it has L2 cache, L1 texture cache, z stencil cache, and color cache. Does that sound right?
Sounds quite right. I wonder though, apart from 1600SP it would also say 4 quad-rops. I thought "everybody" agreed rops would probably be doubled to 32.
 
There's nothing out of the ordinary. But considering this (rv8xx) is supposed to be a radical change, it seems downright tepid.

Based on the interview it's not necessarily "radical change", the "RV770" was mentioned as good starting point, and only one part of the core was specified to be over twice as complex as RV770's, the (main(?)) scheduler.
 
Based on the interview it's not necessarily "radical change", the "RV770" was mentioned as good starting point, and only one part of the core was specified to be over twice as complex as RV770's, the (main(?)) scheduler.

The scheduler could conceptually be in that scheduler block. :???: They are not to scale after all....
 
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