My point was basically "we know how much 512b GDDR5 will consume, just look at R700, increase it for higher memory clock speeds and reduce it by whatever the PCIe bridge takes. And maybe also 1GB vs 2GB". So even assuming (unlikely) that NV engineers are too dumb to look at a GDDR5 specsheet, it's not hard to see that it's not such a big deal. Either way this is just a detail and it's best we don't focus too much on it...
Too dumb to look at the spec sheet? That strategy served their packaging people well....
All I am trying to say is that if they switch to GDDR5 from GDDR3 while keeping the width the same, power used by the chip for memory IO will go up. From what I have seen on power, it is hardly a 'detail'. The only comparison you can reasonably make between the two architectures at the same width is the 4850 and 4870, and there is quite a difference there.
Forget the X2, that is 256 to 512, sort of. In the case of the hypothetical GT200 vs GT300, the width stays the same, making the ATI cards a much better comparison.
With regards to GT300 in general, Charlie, the problem is you made a whole bunch of bizarre claims in your GT300 article that are nearly certainly horribly wrong. And that's before we consider non-GT300 tidbits you got wrong, such as:
- Process node density. The node numbers are marketing, 55nm is not 0.72x 65nm it's 0.81x, the real density is available publicly and you should only look at that. Density from a full node to another full node is not fully comparable, but you should at least be looking at the kgates/mm² and SRAM cell size numbers.
Yes, I did simplify on purpose, I wasn't trying to do a doctoral level course on semiconductor manufacturing. If you want to go down that path, how about analysing how closely each chip follows those specs? Minimum size is an industry joke made for bragging rights. Try comparing a real chip made on TSMC 40 to Intel's 45 to see how closely the specs are followed when it matters.
Since there are specs, more specs, and reality, I use the quoted widths as an approximation. If you take into account all the DFM rules for each different application, you could write a very think book on the topic before you even got to the point.
However, if you think minimum drawn size on a process has anything to do with the end result chip, feel free to break out the electron microscope and show us. I did when I wanted to prove something.
- "The shrink, GT206/GT200b" - I can tell you with 100% certainty GT206 got canned and had nothing to do with GT200b. However it still exists in another form
- GT212 wasn't a GT200 shrink, it had a 384-bit GDDR5 bus and that's just the beginning. You have had the right codenames and part of the story of what happened for some time, which is much more than the other rumor sites/leakers, but you don't have the right details.
I may have some of the details wrong, but then again, the code names keep changing, getting re-used and modified. It is a bitch to keep track of them if you don't have a person you can directly ask. I try and keep as up to date as I can.
- "Nvidia chipmaking of late has been laughably bad. GT200 was slated for November of 2007 and came out in May or so in 2008, two quarters late." - it was late to tape-out, but it was fast from tape-out to availability (faster than RV770). G80 was originally aimed at 2005 for a long time but only taped-out in 2006, does that make it a failure? For failures, look at G98/MCP78/MCP79 instead.
- etc.
I am not sure why this is relevant to the discussion at hand, but yeah, I know. I know all about the MCP79, what a joke that was. I mean, look at the MacBookPro's Hybrid mode....oops.
Seriously though, if you want to list NV failures, this could be a very long thread.....
Then we get to GT300:
- "The basic structure of GT300 is the same as Larrabee" - if that's true, you need scalar units for control/routing logic. That would probably be one of the most important things to mention...
Slight overgeneralization for the audience I am writing for. Would you be happier if I said, "Both have a number of general purpose cores that are replacing fixed function units in order to be more efficient at GPU compute tasks, but give up absolute GPU performance in order to do so."?
- "Then the open question will be how wide the memory interface will have to be to support a hugely inefficient GPGPU strategy. That code has to be loaded, stored and flushed, taking bandwidth and memory." - Uhh... wow. Do you realize how low instruction bandwidth naturally is for parallel tasks? It never gets mentioned in the context of, say, Larrabee because it's absolutely negligible.
Yes I do, that is the whole point of SIMD you know. Who said anything about instructions though? You need to load the data, and that usually is an order of magnitude more bandwidth. Am I missing something, or are you putting words in my mouth? Did I mention instructions vs data anywhere?
- "There is no dedicated tesselator" - so your theory is that Henry Moreton decided to apply for early retirement? That's... interesting. Just like it was normal to expect G80 to be subpar for the geometry shader, it is insane to think GT300 will be subpar at tesselation..
Yes. The whole point is that if you have X shaders, and tesselation takes 10% of X, that leaves you with 90% of X to do everything else. That means if you flip on tesselation, your performance WILL go down.
If you have dedicated hardware to do it, you flip it on, and performance is more or less the same. Is that so hard to comprehend? I said that pretty clearly.
- " ATI has dedicated hardware where applicable, Nvidia has general purpose shaders roped into doing things far less efficiently" - since this would also apply to DX10 tasks, your theory seems to be that every NV engineer is a retard and even their "DXn gen must be the fastest DXn-1 chip" mentality has faded away.
No, I think the engineers are very smart. Management on the other hand seems to be..... well... not so smart. They repeatedly mouth off is stupid ways, and the surrounding yes-men make it happen no matter how daft the plan is. There is no free thought at Nvidia, it is a firing offense.
When JHH says X, they make X happen no matter how much it costs, or how much it hurts in the long run. Go back and talk to the financial analysts, ask them what NV was promising them for last summer, this summer, and next. Then look at the architectures of the GT200 and GT300. See a resemblance?
Then stop and think about how the GPGPU market did not comply with the wished of Nvidia. The architecture is there, the market isn't. If the market had followed JHHs prognostications, it would have been much better for the company.
If I took the time to list all this, it's so that I don't feel compelled to reply in this thread again too much. It's important to understand that it's difficult to take you seriously about NV's DX11 gen when that's your main article on it, and I wasn't even exhaustive in my list of issues with it and didn't include the details I know. Their DX11 gen is more generalized (duh) but not in the direction/way you think, not as much as you think, and not for the reasons you think. Anyway, enough posting for me now!
I don't always print what I know. I didn't print when ATI got R870 silicon back, nor did I print up when it taped out. Hell, I didn't even print up the specifics of the chip, but I do know them. To a lesser degree, I know the NV specs.
I also know I generalize. I can't print out the entire history of the semiconductor industry in every article. Sorry.
All this said, in 2-3 days, you will understand what trouble NV is in. Maybe I will drop you a hint Monday.
-Charlie
