[PVR_Extremist]

A number of years ago the general consensus of opinion was that IMR would hit some kind of "technological wall" with respect to memory bandwidth and clock speed. This was an argument that PowerVR fans (including myself, truth be told) used to proport PowerVR technology as the eventual winner in this race.

Clearly to date at least this has not happened. Credit to nV and others who have employed various techniques to use their available bandwidth more efficiently (whilst managing to get hold of faster more capable RAM also).

My question:

Is there still some kind of "technological wall" which will hamper IMR performance in the future?

My personal opinion is that nV and others will lean towards a hybrid config further optimising their bandwidth saving techniques but not fully going towards a tile based deferred rendering solution.

Also,

Are "other" companies actively pursuing Tile based deferred rendering in "future projects"? If they are how long do you think PowerVR hold the advantage with respect to experience and capability in that area of technology?

Regards

Tino

[mboeller]

see below the thread "Intel's new graphics core" for answers.

[PVR_Extremist]

I saw that thread but in all honesty don't really consider Intel much of a competitor in the 3D market.

And it dont answer any of my other questions

[mboeller]

Originally Posted by PVR_Extremist

I saw that thread but in all honesty don't really consider Intel much of a competitor in the 3D market.

And it dont answer any of my other questions

Sorry; but I have no answers myself. I had hoped that you see Intel as an "player" in the 3D-chipset arena. I'm not sure myself if this new Intel-chipset will help IMG; but it is better when 2 companies have an deferred rendering architecture instead of only one.
If Intel would have used this core in the 850E-chipset too, then they would have been a force to recognisse, simply because the 4,2GB/sec bandwidth would have been enough for an deferred renderer to shine ( and maybe even outshine the nForce chipset / MX400 class ).

I hope that Intel will use this graphics-core in all new chipsets to improve the 3D-performance of all new chipsets. If that happens then IMG has an easier time when new 3D features come up in new DirectX / OpenGL versions.

[pascal]

I think game developers also helped to avoid the "technology wall" by never developing a game that will not run well with the current IMR.

Imagine the games we could have if developers had good deferred render available.

The trick is that we get used to the limitations imposed by IMR.

Soon or later they (hardware and software developers) will have to think seriouslly about deferred rendering.

[Tahir2]

We are approaching a level where polygons will become smaller than the size of pixels.. then even deferred rendering will become obsolete, surely?

Is there still an advantiage of using deferred rendering when polygons are so small?

[MfA]

Rendering is not necessarily deferred with tiling, the scene is just rendered in tile order ... there's a difference.

[PVR_Extremist]

Originally Posted by pascal

Soon or later they (hardware and software developers) will have to think seriouslly about deferred rendering.

When? Why? Does this infer that the big 2 already have deferred rendering somewhere in their roadmap?

[pascal]

I dont know anything about roadmaps and this is just a gamer´s guess (or hope).

In 2 or 3 years we will start to see some DX9 games (many levels of multipass), and the hardware developers will have a good .09 micron process available (means DX9 to the mass). The main competition will be the $80 to $150 DX9 card which is cost sensitive. To keep cost down with high performance a deferred rendering will make sense. It will save bandwith and fillrate.

[Ty]

Originally Posted by pascal

I dont know anything about roadmaps and this is just a gamer´s guess (or hope).

In 2 or 3 years we will start to see some DX9 games (many levels of multipass), and the hardware developers will have a good .09 micron process available (means DX9 to the mass). The main competition will be the $80 to $150 DX9 card which is cost sensitive. To keep cost down with high performance a deferred rendering will make sense. It will save bandwith and fillrate.

Well that's pretty much the line of reasoning that Tino refers to that PVR fans have used in the past. And obviously for one reason or another, it just has not come to pass.

[PVR_Extremist]

Originally Posted by Ty

Well that's pretty much the line of reasoning that Tino refers to that PVR fans have used in the past. And obviously for one reason or another, it just has not come to pass.

I was just going to say that

I can see Tile Based Deferred Rendering making more sense from a cost point of view. Indeed it doesnt cost alot today. Then again what we have available now from IMGTEC isnt a GF4ti4600 in performance either.

So my original questions still stand....

[pascal]

Not exactlly the same reasoning.

What if Kyro II had a DDR memory and 3 or 4 pipelines?
I think it could still be cheap and much faster than any other card in the same price range.

edited: what I am trying to say is "the same price range with much better performance" not "the same performance in the same price range".

[Saem]

Actually, Intel using a deffered + tile architecture, is far more important than IMG help bring to the PC arena. One thing to note is the fact that the i810 chipsets with their integrated core are in about 50% of desktops, IIRC. It was in a survey done not too long ago, it was discussed in the forums as well.

With that said, I think we'll see more of the same, with i845G. If this is the case then, guess where a lot of game makers will target their games?

[Humus]

Ok, hit me, but I think that IMR is the way to go. Not only can you get decently close speedwise with HyperZ like implementations but you can also get useful information in the form of the depth values for shadowmapping and other effects. IMR's may also give you occlusion query information.

[Reverend]

It's simple really - faster memory as well as more games appear to be CPU limited.

[MfA]

Noone likes occlusion queries but software developers, and now that they have it Ive only seen it put down on the GDalgorithms :) (Demo's are nice, but I prefer the impressions from game developers.) As long as you use immediate mode rendering in its present form its the only way to do finegrained occlusion culling, granted ... but its a pretty damn sucky way, would be much better if the hardware had access to bounding volume information itself IMO.

Getting Z values for a shadow buffer is hardly a problem for a tiler, just a variation on rendering to a texture.

[Ty]

Originally Posted by pascal

Not exactlly the same reasoning.

What if Kyro II had a DDR memory and 3 or 4 pipelines?
I think it could still be cheap and much faster than any other card in the same price range.

edited: what I am trying to say is "the same price range with much better performance" not "the same performance in the same price range".

Well the whole "What if?" line of arguments have also been done to death previously as well. "What if the Neon250 came out on time? What if memory prices didn't drop for the original 3Dfx Voodoo1? What if the Kyro had the benefit of mass production? Etc. etc." We all know that on paper deferred renderers have great benefits. The problem is that so far, no one has proved that one can come out at, "the same price range with much better performance" - speaking of the top end here where IMR's are supposedly hitting the bandwidth ceiling.

[MfA]

If people would stop trying to proove the negative others could stop presenting "what if" scenarios.

[Ty]

Originally Posted by MfA

If people would stop trying to proove the negative others could stop presenting "what if" scenarios.

There's no 'proving of the negative' here because you can't logically prove a negative. We're waiting for proof of the assertion that IMRs will not be able to keep up with bandwidth demands and that deferred renderers will take over.

[arjan de lumens]

Originally Posted by PVR_Extremist

My question:

Is there still some kind of "technological wall" which will hamper IMR performance in the future?

Still memory bandwidth. So let's take a look at what the maximum possible memory bandwidth into a single-chip GPU might be. This bandwidth is determined mainly by 2 factors:

• Width of memory bus, in number of pins
• Datarate per pin of memory bus

For a Geforce4, you get 128 bits * 650 MHz = 10.4 GBytes/sec. But the ultimate maximum? The maximum bus width is obviously no less than 256 bits (P10, Parhelia) - with flip chip packaging, pin counts of up to several thousands is possible, so I'd estimate that a 1024-bit (external!) bus is possible (though certainly expensive as hell). For the datarate, Rambus QRSL signalling permits a datarate of 1.6 GBit/s per pin - I'm not aware of any other scheme that offers comparable per-pin datarates.

This amounts to a (rather hypothetical) maximum of about 200 GB/s, barring cost and signal integrity issues. Which is about 20 times what Geforce4 has. So IMRs won't run into any hard limits anytime soon - about 6-7 years away, according to Moore's law. At which time eDRAM may have gotten cheap enough to take over for external memory solutions...

[Althornin]

Originally Posted by Ty

There's no 'proving of the negative' here

Hence the word "trying" in MFA's post....

[DemoCoder]

The DreamCast was a platform where every single developer knew they were coding for a deferred architecture and yet the games developed did not blow away games on IMR systems. You can't blame it on the developers.

The IMR systems to date have been bottlenecked in other areas such as fillrate and geometry performance. It's all well and nice that they don't need 500 Mhz DDR to work, but they skimped on the fillrate and T&L.


Developers can't very well push 20x overdraw/multipass with massive architecture if the CPU/T&L/fillrate of the unit can't handle it.

But of course, many people have been harping on this for years while all the naysayers bashed IMR vendors for boosting fillerate and wasting efforts on T&L.

[Althornin]

Originally Posted by DemoCoder

The IMR systems to date have been bottlenecked in other areas such as fillrate and geometry performance. It's all well and nice that they don't need 500 Mhz DDR to work, but they skimped on the fillrate and T&L.

dont you mean "the TBR/Deferred rendering systems to date...."
And if so, then i mostly agree with what you have to say.

[Entropy]

Originally Posted by PVR_Extremist

My question:

Is there still some kind of "technological wall" which will hamper IMR performance in the future?

My personal opinion is that nV and others will lean towards a hybrid config further optimising their bandwidth saving techniques but not fully going towards a tile based deferred rendering solution.

To adress the original question, there obviously doesn't seem to be any hard limits. The performance development has been quite predictable, with greater increases when the memory subsystem has gotten a factor of two architectural boost.

Generally speaking, graphics is well suited to parallell processing which would seem to point us in the general direction of tilers, though not necessarily deferred renderers.

Looking at the trends of game graphics, we see
1. Increased polygon count
2. More complex environment = more overdraw
3. More work per pixel

1 would seem to favour IMRs, 2 would seem to favour DMRs and 3 could go either way with a theoretical favour for DMRs but with problems too.

(As usual, programmers will adapt to the limitation of the platforms available, so for DMRs to take over the market, they have first got to outperform IMRs on their own turf so to speak, as IMRs set the standard. But that is market dynamics, not technology.)

As has been pointed out, memory bandwidth would seem to be the factor that places the upper bound on IMR performance. (And for that matter DMRs, but at a slightly different point and for slightly different reasons. Data flow is _always_ limitid by bandwidth. doh.) This will be the year when 256-bit DDR takes off, we can expect the usual clock ramps, and we have 4-bits-per-pulse tech waiting in the wings if necessary. Extrapolating, this should take us to a nominal 100GB/s within five years or so. Not too shabby, but not too exciting either, as it is only a factor of five after all, and the estimate is not pessimistic. However, that is time enough for GPUs to be able to carry sizeable amounts of memory on-chip, which is one way of to reduce the dependance on off-chip memory bandwidth.

The problem for IMRs is that the bandwidth development is still pretty slow compared to the overall performance increases we could envision in that time frame. So we need to get smarter with how we use it, and indeed we are, using different techniques to both reduce unecessary rendering examplified for instance by HyperZ, and to reduce unnecessary polygon load with Matrox's depth adaptive tesselation as the latest but certainly not last example. Peering deeply into the crystal ball in order to predict the farthest front of technology (five years or so) we should be able to expect doubled rendering performance every year during that period.

(So extrapolating from the latest benchmark/demos Commanche4 and CodeCreatures, in five years we will be able to marvel at large numbers of nicely modelled static trees rather than either or. Oh joy.)

Deferred rendering is attractive due to the fundamental reasonableness of only rendering what is actually seen. But it doesn't remove all bottlenecks, and introduces some extra work of its' own, and the real question is whether the bottleneck it removes is so much more limiting than the next bottleneck down the line + DMR overhead.... If not, extending and improving IMRs may be more practical in an application environment where IMR limitations are taken into account in graphics engine development and applications.

Entropy

[SA]

Probably the major memory bandwith advantages for tiling comes from the locality of reference of the depth and frame buffer information more than from deferred rendering as such. Since the depth and frame buffer information for a tile can fit entirely on the chip, the z's and frame colors stay on chip for all the depth and color computations. This allows very high on-chip memory bandwidth to be used much like edram solutions, only without the large on-chip memory requirements.

Deferred rendering is an added bonus for memory bandwidth since it primarily reduces texture bandwidth which is generally less intensive at the moment. In the future, it will eliminate wasted pixel shader computations which will become critically important.

However, by using a combination of compressed z's, hierarchical z buffering, and multiple z checks per pixel, combined with application driven deferred rendering (an unshaded pass followed immediately by a shaded pass), IMRs get almost all of the memory bandwidth savings of a deferred rendering tiler without any of its problems (API incompatibilities, etc.).

In the future, z queries will help reduce memory bandwidth even more (though they work equally well for both TBRs and IMRs)

The memory bandwidth "wall" is a bit illusory. There are many memory bandwidth technologies yet available. 256 bit buses are currently popular. Embedded RAM of one type or another is still a bit off but holds a lot of promise. MCM's open up many possibilities. Frequencies continue to climb. Better caching mechanisms, especially for geometry are on the horizon. On chip tessellation and displacement maps will also help in the geometry bandwidth department.

Chip designers forecast as best they can what the technology and cost structure of memories will be like when their design is built a couple of years out. Different 3d vendors take different memory approaches, but they all create a design that provides the memory bandwidth to meet their goals, using whatever they think is going to be the least expensive and best approach at the time of product launch. That's their job of course.

If any remember my posts of the past, they know that I like tilers. However, it is no coincidence that all of the major 3d hardware vendors at the high end including Nvidia, ATI, 3dlabs, and Matrox all use immediate mode renderers. Their engineers are all very aware of the tradeoffs between tiling architectures and IMRs and they have chosen IMR's for a reason. So it may seem that I prefer IMRs. I do not. I simply prefer whatever works best. Other than that I have no preferences either way. If TBRs really are the fastest solution and can produce the highest quality, high-end 3d graphics then they must demonstrate it with purchasable products the way IMRs have been doing for some time.

I think if TBR was so clearly the way of the future the way high precision color, programmability, and high quality AA are, then vendors would have pushed for the API changes to really support it long ago and would now all be using it. The fact that all the largest players in the market have not done this means their engineers feel there are better alternatives, and until there are purchasable products to demonstrate otherwise, they have not been proven wrong.

I for one would really like to see a fully maxed out TBR with all the pixel pipelines, external memory bandwidth (plenty of this is still needed of course), programmability, vertex shader performance, high quality AA, etc. needed to fully show what the approach is capable of. A real contender on the TBR side would be interesting to say the least.