[fellix]

Ivy Bridge Architecture Exposed

Some overhauls in brief:

- dynamic micro-architecture resource allocation between single-thread and SMT workloads;
- 2x faster FP/INT divider (again);
- a bunch of ISA improvements, like the MOV op's now actually employs the advantage of PRF;
- digital random number generator;

[Otto Dafe]

MOV operations can now take place in the register renaming stage instead of making it occupy an execution port. The x86 MOV instruction simply copies the contents of a register into another register. In Ivy Bridge MOVs are executed by simply pointing one register at the location of the destination register. This is enabled by the physical register file first introduced in Sandy Bridge, in addition to a whole lot of clever logic within IVB. Although MOVs still occupy decode bandwidth, the instruction doesn't take up an execution port allowing other instructions to execute in place of it.

Does this do away with LHS stalls, or am I just being simple?

[rpg.314]

LHS removal needs deterministic aliasing determination.

AFAICS, this just removes reg-reg mov instructions.

[hkultala]

Originally Posted by fellix

Ivy Bridge Architecture Exposed

- 2x faster FP/INT divider (again);

Not exactly again.

In penryn they halved divider's latency. (and also got same improvement in throughput?)

In Ivy bridge they are only improving throughput, not latency.

So they are either adding another divide unit, or pipelining the existing one.

(is the current divider pipelined at all? does one divide instruction block the divider until the operation is finished?)

[Novum]

The divider is not pipelined in sandy bridge and all other (x86) processors I know.

But I don't know if that's even possible. It seems like they actually want to introduce a second divider at the same port.

[fellix]

The division/sqrt logic in Intel's architectures prior to Penryn was very latent. I think Intel was catching with AMD in this regard for some time, and now should even exceed the norm.
Dothan and P4 were still twice slower in FDIV latency, compared to all the AMD's architectures since K7!

[entity279]

AMD *does* pipeline its dividers, at least starting with Barcelona

[mczak]

Originally Posted by entity279

AMD *does* pipeline its dividers, at least starting with Barcelona

From the optimization manual, doesn't really look pipelined to me. The latency numbers are just slightly higher than the throughput, I don't know if that would even qualify for partially pipelined looks like a very minor "overlap".
(That said if you just want to increase the throughput and not the latency I'd guess partially pipelined would be the way to go for IVB.)


Edit: actually something different could be meant for "twice the throughput". Note that all these newer intel chips have the same latency and throughput for DIVPS and DIVSS (which gets me to another idea would be neat if you could use all 4 divide subunits for those scalars...) but the latency/throughput for the 256bit version is twice that (or half respectively) so the chip apparently only really has a 4x32bit divide unit not 8x32bit - intel could simply expand the divide unit to the full 256bit to claim double divide throughput and it would make sense I think (I can't see why 256-bit AVX optimized code would have less divisions comapred to other instructions relative to the same code optimized for 128bit SSE). Of course it would only matter for AVX code not a single bit for int/sse2/fp.

[Mendel]

Is there any word on whether there is going to be a 6 core or even 8 core Ivy Bridge CPU for LGA 1155?

[mczak]

Originally Posted by Mendel

Is there any word on whether there is going to be a 6 core or even 8 core Ivy Bridge CPU for LGA 1155?

Haven't seen anything but I'm quite convinced "no".
A 6 core (not to mention 8) LGA 1155 IVB would completely kill LGA 2011 (Sandy-Bridge-E) as the enthusiast platform. Apparently intel doesn't feel like releasing 8 core Sandy-Bridge-E (as Core i7-3xxx) even if the corresponding Xeons have 8 cores.
Maybe if intel would change their mind a 6 core IVB-1155 could come later - but I guess by that time we're looking at Haswell...
But since the enthusiast platform lately is about 2/3 of a generation behind mainstream things might continue like this - 8 core IVB for enthusiast platform (LGA2011) in about a year (giving it a huge performance lead over mainstream at the time of introduction), followed by 6-core Haswell for mainstream platform (reducing that lead to almost nothing again...). I pulled that speculation out of thin air though .

[fellix]

Originally Posted by Mendel

Is there any word on whether there is going to be a 6 core or even 8 core Ivy Bridge CPU for LGA 1155?

Some time ago, a BIOS update from GigaByte was found to contain a possible support for 6-core CPU ID on LGA1155, but nothing more than that. I personally doubt there would be any SKUs for LGA1155 with more than four cores especially in the face of the fact, that LGA2011 for desktops will be capped to 6-core models for the foreseeable future.

[Mendel]

Well, at least there will be some sort of upgrade path from 2600k with socket 1155. I think many were under the impression that there will be 2700k and then that´s it for 1155 and if you want to upgrade then socket 2011 it is. Whether or not it´s an upgrade path that makes sense though...remains to be seen.