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Old 21-Nov-2011, 18:42   #151
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Originally Posted by ToTTenTranz View Post
It's none of that if the purpose is to make an APU that really discards a mid-high end discrete GPU.

Unless you think adding a third memory channel is more expensive than an entire MXM card...
But the bulk of the market remains integrated graphics. If you want a competitive product for this target, triple channel isn't realistic.

Well, I suppose you could always design a 3-channel APU and let motherboard makers produce boards with only 2 channels for cost-sensitive markets. You'd need a bigger die and more complex socket, but maybe not significantly more expensive boards for OEMs that don't want them.
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Old 21-Nov-2011, 19:11   #152
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But the bulk of the market remains integrated graphics. If you want a competitive product for this target, triple channel isn't realistic.

Well, I suppose you could always design a 3-channel APU and let motherboard makers produce boards with only 2 channels for cost-sensitive markets. You'd need a bigger die and more complex socket, but maybe not significantly more expensive boards for OEMs that don't want them.
Of course AMD wouldn't create a 3-channel solution for 500€ laptops..

It's a matter of either creating a platform for that end or not.
Yes, the socket would have to be more complex, but AMD coud sell APUs with 2 or 3 channels and motherboards with 2 or 3 channels, using the same sockets.

A 28nm APU with dual-module Piledriver, Juniper-ish iGPU and efficient 3-channel memory controller would nail all the 800-1200€ laptop designs that are today ruled by Sandybridge + nVidia GF108/GF106 combos.
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Old 07-Dec-2011, 07:59   #153
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Ivy Bridge GT1 @ Coolaler:
http://www.coolaler.com/showthread.php?t=278192&page=11

HD2500 15.26.0.2500
900 Mhz Vantage GPU: 1150
1500 Mhz OC Vantage GPU: 2022
900 Mhz? 3DM11: P351 (263 graphics-score) compare

Circle @ D3D-AF-Tester:


So HD 4000 might go against HD 6450?
16 EUs @ 1300MHz (Mobile-i7) should deliver ~330GFLOPs(@MAC)?

Last edited by AnarchX; 07-Dec-2011 at 08:37.
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Old 07-Dec-2011, 08:18   #154
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Originally Posted by AnarchX View Post
Ivy Bridge GT1 @ Coolaler:
http://www.coolaler.com/showthread.php?t=278192&page=11

HD2500 15.26.0.2500
900 Mhz Vantage GPU: 1150
1500 Mhz OC Vantage GPU: 2022
900 Mhz? 3DM11: P351 (263 graphics-score) compare

Circle @ D3D-AF-Tester:


So HD 4000 might go against HD 6450?
16 EUs @ 1300MHz (Mobile-i7) should deliver ~330GFLOPs(@MAC)?
Nice circle there.

For mobile, even the dual core should have HD4000.
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Old 05-Jan-2012, 18:23   #155
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Does anybody see more than 6 SIMD engines (384 SPs) in that die shot of Trinity?

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Old 05-Jan-2012, 18:31   #156
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No, I don't. I think AMD promised a 50% increase in FLOPS, so that's strange. Do they intend to push clocks 56% higher than in Llano?

Well, come to think of it, that would only be about 940MHz, which sounds doable, at least in Turbo mode. Still a bit odd.
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Old 05-Jan-2012, 19:16   #157
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50% more in Flops? When did they promise that? I can only remember this pic in the bottom of the page:

http://www.anandtech.com/show/4444/a...pu-a8-3500m/13
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Old 05-Jan-2012, 19:57   #158
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They "promised" 30 % higher GPU performance and 715 GFLOPs (but those Llano numbers are wrong)
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Old 05-Jan-2012, 19:58   #159
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Here you go: http://www.xbitlabs.com/news/cpu/dis...o_Company.html
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Old 05-Jan-2012, 19:58   #160
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50% more in Flops? When did they promise that? I can only remember this pic in the bottom of the page:

http://www.anandtech.com/show/4444/a...pu-a8-3500m/13
You're right, Llano indicates ~600 GFLOPS, Trinity indicates ~1100 GFLOPS, making the difference ~78% according to that chat. Obviously there's room for interpretation based on how thick the line is and where the labels are placed, but that's how I see it anyway.
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Old 05-Jan-2012, 20:00   #161
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Does anybody see more than 6 SIMD engines (384 SPs) in that die shot of Trinity?

Is Trinity supposed to have a new revision of the BD architecture? I think there's an additional SRAM bank to the instruction pre-decode array in the front-end, compared to the current revision of BD.
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Old 05-Jan-2012, 20:02   #162
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Is Trinity supposed to have a new revision of the BD architecture? I think there's an additional SRAM bank to the instruction pre-decode array in the front-end, compared to the desktop revision of BD.
Trinity is Piledriver-based.
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Old 05-Jan-2012, 20:04   #163
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Yes Trinity use the Piledriver core.
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Old 05-Jan-2012, 20:16   #164
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You're right, Llano indicates ~600 GFLOPS, Trinity indicates ~1100 GFLOPS, making the difference ~78% according to that chat. Obviously there's room for interpretation based on how thick the line is and where the labels are placed, but that's how I see it anyway.
No, I think 1100 GFLOPs is for that ominous "2013 platform" (Trinity successor). If you look very closely, you see a slight bend in the line just above the 800 mark. So Trinity seems to be in the 800-850 range of that chart.
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Old 05-Jan-2012, 20:50   #165
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No, I think 1100 GFLOPs is for that ominous "2013 platform" (Trinity successor). If you look very closely, you see a slight bend in the line just above the 800 mark. So Trinity seems to be in the 800-850 range of that chart.
Ahhh, yes I do see that. Ok, so Llano is ~600, Trinity is somewhere around the 850 mark. That's not too far off from 50% depending on the rounding error on Llano. I mean, if we look at the backside-kink of that line, Llano might be ~550

The real deal is that's just a really terrible graph, and given the multiple sources posted above, is obviously wrong and should be dismissed.
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Old 05-Jan-2012, 20:51   #166
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Scaled comparison of Llano and Trinity, using the I/O pads on the left side for reference:



Some observations on the layout of the SIMD multi-processors -- the placement of the register file banks in the ALU array is different in Trinity, as well as the whole layout of the texture unit.

Here are the differences (so far) on the CPU side -- BD vs. Piledriver cores:



Those banks are most probably the pre-decode bits (used for the BTB, branch selector, end bits & etc.), that AMD has been using ever since the first K7 architecture to aid the instruction decode flow. And since these are located in the branch prediction area of the front-end block, I guess AMD is aiming at improving namely this aspect of the architecture.
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Old 05-Jan-2012, 21:04   #167
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They "promised" 30 % higher GPU performance and 715 GFLOPs (but those Llano numbers are wrong)
So it's 20% more CPU perf + 30% more GPU perf = 50% more perf!

I am personaly specualting there will be 2 x 256 bit FMAC in each module, so that would be doubling peak Flops and then a clock boost on top. So over 200GFlops from the CPU alone, so the GPU won;t have to clocked that high to reach the projected total GFLOP values. But since I might be the only one thinking that, I could be very wrong.
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Old 05-Jan-2012, 21:11   #168
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So it's 20% more CPU perf + 30% more GPU perf = 50% more perf!

I am personaly specualting there will be 2 x 256 bit FMAC in each module, so that would be doubling peak Flops and then a clock boost on top. So over 200GFlops from the CPU alone, so the GPU won;t have to clocked that high to reach the projected total GFLOP values. But since I might be the only one thinking that, I could be very wrong.
It is (or at least it was supposed to be) 50% more FLOPS on the GPU for 30% more performance in actual games, and up to 20% more performance on the CPU side for common applications.

The FPU appears to be largely unchanged, so no 256-bit FMACs.
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Old 05-Jan-2012, 21:15   #169
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What strikes me as odd is the GPU in Trinity. The 6 VLIW4(?)-SIMDs only take up ~as much space as the 5 SIMDs in Llano, yet the "uncore" of the Trinity GPU is MUCH larger and appears to be the only reason why Trinity is larger than Llano. Any idea what all that space is used for? Larger cache(s) to reduce memory bandwidth bottlenecks?
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Old 05-Jan-2012, 21:29   #170
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Compared to the ALU blocks, the rest of Llano's GPU is 3,78-times bigger. But 4,75-times bigger for Trinity (rough numbers). I would expect exactly opposite numbers...
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Old 05-Jan-2012, 21:38   #171
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Compared to the ALU blocks, the rest of Llano's GPU is 3,78-times bigger. But 4,75-times bigger for Trinity (rough numbers). I would expect exactly opposite numbers...
Would you? Cayman had fewer shaders than Cypress, but was significantly bigger. And (presumably) it didn't have has much redundancy for vias and stuff.
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Old 05-Jan-2012, 21:47   #172
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Would you? Cayman had fewer shaders than Cypress, but was significantly bigger. And (presumably) it didn't have has much redundancy for vias and stuff.
Cayman had 24 SIMDs vs. Cypress' 20. So even though that's a few less ALUs, that's 20% more texture units, L1 cache, LDS memory, etc.
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Old 05-Jan-2012, 23:03   #173
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Cayman had 24 SIMDs vs. Cypress' 20. So even though that's a few less ALUs, that's 20% more texture units, L1 cache, LDS memory, etc.
The GPUs of Trinity vs. Llano exhibit the exact same ratio as Cayman vs. Cypress (trading five VLIW5 vs. six VLIW4 SIMD engines).
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Old 06-Jan-2012, 00:07   #174
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Cayman had 24 SIMDs vs. Cypress' 20. So even though that's a few less ALUs, that's 20% more texture units, L1 cache, LDS memory, etc.
Yep, that was my point.
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Old 06-Jan-2012, 01:18   #175
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I am personaly specualting there will be 2 x 256 bit FMAC in each module, so that would be doubling peak Flops and then a clock boost on top. So over 200GFlops from the CPU alone, so the GPU won;t have to clocked that high to reach the projected total GFLOP values. But since I might be the only one thinking that, I could be very wrong.
The present desktop BD's cannot keep the FPU fed with data. What exactly would be the point of doubling the peak flops when you are so bandwidth-starved that it would never increase real-world performance?
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