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Old 07-Dec-2012, 16:31   #101
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Wow, we are already in the speculation zone for what will come in 2015.

Given that we know almost nothing about what's coming in a quarter... that's a nice try.
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Old 07-Dec-2012, 20:47   #102
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Originally Posted by iMacmatician View Post
Apparently not all of them will.

And this report is under "Analysis."

If this report is true, then I'm guessing the Maxwell lineup may be something like the G80, G92, and GT200.

"Maxwell Prime": 28 nm, Q1 2014, 400-450 mm^2, 384-bit bus, game performance ≥ GeForce version of Tesla K20/K20X.
"Maxwell Lite": 20 nm, Q4 2014 or whenever 20 nm realistically shows up, 250-300 mm^2, ≥256-bit bus, performance ≈ Maxwell Prime depending on bandwidth bottlenecks?
"Big Maxwell": 20 nm, 2015, 500-550 mm^2, 512-bit bus, focusing on compute.
I don't know what the V I from S|A is smoking but TSMC will have 20nm in full production in 2013 so no way is Maxwell going to be either on 28nm or released in 2015.

TSMC Lays Process Technology Roadmap Out.
http://www.xbitlabs.com/news/other/d...admap_Out.html

TSMC says it's ready for 20-nm designs
http://www.eetimes.com/design/eda-de...sign-says-TSMC

20nm Technology
http://www.tsmc.com/english/dedicate...ology/20nm.htm

TSMC sketches finFET roadmap
http://www.techdesignforums.com/blog...infet-roadmap/

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Old 07-Dec-2012, 21:49   #103
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I think performance at 20/22 nm without FDSOI or FinFETs will be a dud (ie. not competitive with just sticking to 28 nm). TSMC seems to be the only one trying it.
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Old 08-Dec-2012, 04:11   #104
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I think performance at 20/22 nm without FDSOI or FinFETs will be a dud (ie. not competitive with just sticking to 28 nm). TSMC seems to be the only one trying it.
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TSMC's 20nm process technology can provide 30 percent higher speed, 1.9 times the density, or 25 percent less power than its 28nm technology.
http://www.tsmc.com/english/dedicate...ology/20nm.htm
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Old 08-Dec-2012, 05:15   #105
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Ignore whatever TSMC says on the matter. Poor planar performance from 20 nm transistors is device physics.
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Old 08-Dec-2012, 06:51   #106
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Not to parse PR text too finely, but the statement about TSMC's process is an OR list, not an AND.

It's 30% faster, and 1.9x as dense, and 25% less power.
It's 30% faster, or 1.9x as dense, or 25% less power.

For GPU chips that tend to push things on performance, size, and power, the former list sounds more promising than the latter.
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Old 08-Dec-2012, 07:30   #107
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Doesn't the density increase come in all situations and the only trade off is between speed or power consumption?
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Old 08-Dec-2012, 09:33   #108
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SRAM can use larger cells than the process minimum for performance or reliability reasons.
Logic has tended to scale less than SRAM with each node, and more complex or higher speed logic has shrunk more slowly.
Less regular structures may need extra measures to manufacture, and wires in more complex logic can restrict density improvement.
When increasing for drive strength for FinFETs, extra fins and thus extra area can used to provide more current.

For control of leakage or manufacturability, parts of the chip can use physically larger transistors to reduce leakage and resist variation. Power gates are physically large relative to the rest.
Even with ideal scaling, the leakage and power efficiency issues will require allocating more of the larger transistor budget to more aggressive power control measures.

The smaller gates are physically less able to control leakage. Without a materials change or fundamental change in the structure of the gates, say HKMG or FinFETs that Intel regularly pushes out, shrinking today's tech by a node means headaches.
Intel has been pretty good about getting these difficult transitions done before the problems they solve smack it in the face.
The foundries tend to delay these more fundamental changes by a node, so they get smacked in the face every other node.

One thing I'm curious about with the foundry plans to hop to FinFETs with a 14nm transistor but 20nm metal layer is how this might compare to Intel's historically being somewhat less aggressive in scaling wire density.
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Old 13-Dec-2012, 14:40   #109
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http://videocardz.com/38693/nvidia-s...rce-800-series
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Old 14-Dec-2012, 15:53   #110
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The design isn't even done yet and that site is so self-assured to create even a picture with a supposed SKU name. As a sidenote it is true afaik that NVIDIA contracted TSMC for their 20nm. I just have the weird gut feeling that the supposed "news" that has been plagiarized from one website to the other with an origin of a korean site isn't really mentioned per se in the original source.
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Old 14-Dec-2012, 16:08   #111
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The design isn't even done yet and that site is so self-assured to create even a picture with a supposed SKU name.
They've had names and "specs" for ten 700 series cards on their site for at least half a year now. So I'm not surprised.
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Old 14-Dec-2012, 16:56   #112
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They've had names and "specs" for ten 700 series cards on their site for at least half a year now. So I'm not surprised.
Why do I have the feeling that this upcoming generation was ready loooong time ago but NV and AMD artificially with other intentions delay the launch till Q1-Q2 2013... What is so special about this generation that they need so much time to cook it?

And from this line of thoughts, I wouldn't be surprised that some people have known the specs for quite a while.
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Old 14-Dec-2012, 18:12   #113
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Why do I have the feeling that this upcoming generation was ready loooong time ago but NV and AMD artificially with other intentions delay the launch till Q1-Q2 2013... What is so special about this generation that they need so much time to cook it?
4 or 5 quarters between updates is artificially long?
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Old 14-Dec-2012, 21:39   #114
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4 or 5 quarters between updates is artificially long?
Given that the next generation is on the same process, it's a distinct possibility.
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Old 14-Dec-2012, 23:43   #115
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Given that the next generation is on the same process, it's a distinct possibility.
I think AMD and Nvidia are very close to each other this generation, with no major obvious flaws. New silicon on the same process can only give incremental changes, IMO. I wonder if it's not better waiting for 20nm for the next big push? Maybe just do some clock speed bump and call it a day.
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Old 15-Dec-2012, 00:02   #116
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Originally Posted by UniversalTruth View Post
Why do I have the feeling that this upcoming generation was ready loooong time ago but NV and AMD artificially with other intentions delay the launch till Q1-Q2 2013... What is so special about this generation that they need so much time to cook it?

And from this line of thoughts, I wouldn't be surprised that some people have known the specs for quite a while.
Nvidia probably wants to lead the 700 series with GK110, but they are probably allocating all their current production until special orders and the HPC supply chains are adequately saturated. But also you are probably partially right, there probably isn't a pressing need on Nvidia's end to refresh their current GPU's, given their higher $$$/mm^2 than what they were getting off Fermi dies.
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Old 15-Dec-2012, 00:51   #117
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I think AMD and Nvidia are very close to each other this generation, with no major obvious flaws. New silicon on the same process can only give incremental changes, IMO. I wonder if it's not better waiting for 20nm for the next big push? Maybe just do some clock speed bump and call it a day.
Possible guess predicated on Maxwell turning out to be the chip that puts an on-die CPU:

Wanting to get the hybrid architecture out in time for an HPC deal?
Trying to move to a self-hosting or mostly self-hosting Teslas?
I would figure that Nvidia has a decent idea on how their design would work, but it might help to put the design through its paces sooner rather than later.
There is doubt about the timeliness of 20nm.

This wouldn't require that the consumer boards get Maxwell.
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Old 15-Dec-2012, 06:04   #118
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I will believe if a co processor ARM cpu is used in the gpu, the benefit could only come by the software and instructions used. For me this use look to be a really short term solution when i look the ambition of other actors about it.

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Old 15-Dec-2012, 09:03   #119
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If Maxwell has a timeline that is not served by the possible timing of 20nm, an initial wave on 28nm could a way to reduce risk of further schedul slips.
Having ARM cores implemented could possibly remove one of the notable shortcomings Tesla has against Larrabee, which has CPU cores that are at least capable of running CPU-side code on the board.
Possibly, at some point accellerator board in some eventual future product would just be the motherboard, and Nvidia can remove a competitor's silicon from being a required element to all of its computing products.
CUDA software running on top the driver layer shouldn't care what CPU is running the driver.

It's a possible direction Nvidia could be taking, at least.
If the host was moved on-die, the Tesla board would--with some work akin to a sever version of its Tegra SOC design--look a bit like an ARM shared-nothing dense server board.
What doesn't seem to work yet is a solution for a cache-coherent interconnect, and the RAM pool a GPU would have is too tiny without the much larger capacity DIMM pool the host x86 chip currently provides.
A memory standard like HMC might solve the capacity without sacrificing the bandwidth Tesla currently relies on.
The other thing is the need for an interconnect, since that is something Nvidia has thus far been reliant on the platform hosted by that inconvenient neighbor it has in the compute node.
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Old 15-Dec-2012, 17:56   #120
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Originally Posted by 3dilettante View Post
If Maxwell has a timeline that is not served by the possible timing of 20nm, an initial wave on 28nm could a way to reduce risk of further schedul slips.
Having ARM cores implemented could possibly remove one of the notable shortcomings Tesla has against Larrabee, which has CPU cores that are at least capable of running CPU-side code on the board.
Possibly, at some point accellerator board in some eventual future product would just be the motherboard, and Nvidia can remove a competitor's silicon from being a required element to all of its computing products.
CUDA software running on top the driver layer shouldn't care what CPU is running the driver.

It's a possible direction Nvidia could be taking, at least.
If the host was moved on-die, the Tesla board would--with some work akin to a sever version of its Tegra SOC design--look a bit like an ARM shared-nothing dense server board.
What doesn't seem to work yet is a solution for a cache-coherent interconnect, and the RAM pool a GPU would have is too tiny without the much larger capacity DIMM pool the host x86 chip currently provides.
A memory standard like HMC might solve the capacity without sacrificing the bandwidth Tesla currently relies on.
The other thing is the need for an interconnect, since that is something Nvidia has thus far been reliant on the platform hosted by that inconvenient neighbor it has in the compute node.
With the instructions included in ARM right now, a complete rewrite of it will be needed,... you will not been able to use it as primary " self processor" without loose a lot of efficiency vs use an x86 processors for do the work. So the impact is really limited on what it will cost you in term of developpement, resource used on a gpu. Ofc Nvidia have the possibility to rewrite the software and library for use it on certain purpose, but, is it really efficient outside marketing ? The main problem of CUDA is the efficiency, most of the usage time you win by use it in computing is lost then, by the way you need hardware for re-encode and been able to use the language and library, and then decode and re encode again the result for control them... ( as CUDA is reallly not safe in term of fiability ( specially when you need a lot of precision on the result.. you neeed basically many hardware and cpu usage time for check the results ), And im affraid this will become worst with an ARM processor for it . ( basically you cant use the base of software/instructions/code you use normally, it will be needed to re encode them for it, it push even further the problem of CUDA API/Library by even need to force an other manipulation of the data ). With this direction the approach of AMD and HSA, look more .. safe ( maybe not the word i wanted to use or not the right word, maybe i should say more toughtful ) .

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Old 15-Dec-2012, 18:02   #121
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If Maxwell has a timeline that is not served by the possible timing of 20nm, an initial wave on 28nm could a way to reduce risk of further schedul slips.
Exactly; besides there's not a single reason why NVIDIA wouldn't keep also for Maxwell the Kepler development strategy: mainstream/performance chips first, high end last or amongst the last.

Assuming NV releases GK110 SKUs for the desktop in early 2013 it will be give or take 1 year after the initial first Kepler desktop release of the GTX680. For Maxwell I couldn't imagine how they'd manage to cram the top dog into 28nm without any HUGE risks for such a complicated design. Else keeping a similar trend leaves enough time for 20nm to mature enough for a desktop high end chip after N timeframe and at the same time a direct shrink of all Maxwell chips that had been manufactured under 28nm.

For performance and lower end Maxwell parts 28nm is a viable alternative to release hw ON TIME and the downside is that die area is going to be quite a bit larger than under 20nm later on. Considering in what shape 20nm is supposed to be I wouldn't suggest that despite the larger die area under 28nm manufacturing costs should be noticably higher.

Besides if I'm not reading wrong into that one: http://www.xbitlabs.com/news/other/d...d_of_Time.html

....who's willing to bet that if above is true, it will be an exclusive design decision for NVIDIA?
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Old 15-Dec-2012, 18:15   #122
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Exactly; besides there's not a single reason why NVIDIA wouldn't keep also for Maxwell the Kepler development strategy: mainstream/performance chips first, high end last or amongst the last.

Assuming NV releases GK110 SKUs for the desktop in early 2013 it will be give or take 1 year after the initial first Kepler desktop release of the GTX680. For Maxwell I couldn't imagine how they'd manage to cram the top dog into 28nm without any HUGE risks for such a complicated design. Else keeping a similar trend leaves enough time for 20nm to mature enough for a desktop high end chip after N timeframe and at the same time a direct shrink of all Maxwell chips that had been manufactured under 28nm.

For performance and lower end Maxwell parts 28nm is a viable alternative to release hw ON TIME and the downside is that die area is going to be quite a bit larger than under 20nm later on. Considering in what shape 20nm is supposed to be I wouldn't suggest that despite the larger die area under 28nm manufacturing costs should be noticably higher.

Besides if I'm not reading wrong into that one: http://www.xbitlabs.com/news/other/d...d_of_Time.html

....who's willing to bet that if above is true, it will be an exclusive design decision for NVIDIA?
Now you know why they have not do it, it was purely impossible for Nvidia to bring the GK110 on the first ramp of 28nm in early 2012... completely impossible.., they end with a tesla card who are under the 4Tflops SP ( and 1/3 rate for dp ), at 732 mhz and one 1 SM(x) is disabled ........ something even harder to put in the market of was Fermi. ( K20x have 14SM, K20 have 13 SM.. the architecture have 15SM up.. so one disabled , and Titan have recieve only K20x ( maybe mixed with K20 possibly )

( its a beast, dont misunderstand me, but how they will have been able to adapt this on the consumers cards generation ? .. i dont think they could have do it ).

Nvidia have put a lot force for make the K20(x) possible to use in High computing market... and really this is a real good and shiny experience... but i cant imagine them have do the same in early 2012 as it was maybe previously the plan to use it in "consumer market" ...

I dont know what to think about this xbitlabs article.. first there's many difference between gpu and cpu, and xbitlabs mix both of them, that's a dangerours way as it can make you conclude illusions or desillusions far away of the results. Then, AMD or ATI have been allways the first to use any process and allways do it successfully on gpu side , because their method to aprehend this is clear and is really accurate . They are really realist on this aspect.

Last edited by lanek; 15-Dec-2012 at 18:36.
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Old 15-Dec-2012, 18:20   #123
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Originally Posted by Ailuros
For performance and lower end Maxwell parts 28nm is a viable alternative to release hw ON TIME and the downside is that die area is going to be quite a bit larger than under 20nm later on.
Eh, I don't see it... why would they care about being "on time" if their only competition doesn't?
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Old 15-Dec-2012, 18:44   #124
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Form a consumer point of view: what is the benefit of an additional CPU on the GPU die? We've heard complaints in the past that DirectX adds a lot of inefficiencies compared to consoles, where you program to the metal. Is an on-die CPU something that could help with this? E.g. Take over some work from the main CPU?

Or is it only useful for GPGPU type applications (PhysX?)
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Old 15-Dec-2012, 18:50   #125
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Form a consumer point of view: what is the benefit of an additional CPU on the GPU die? We've heard complaints in the past that DirectX adds a lot of inefficiencies compared to consoles, where you program to the metal. Is an on-die CPU something that could help with this? E.g. Take over some work from the main CPU?

Or is it only useful for GPGPU type applications (PhysX?)
Not an ARM based one, as basically you will need to code the instructions for allow this cpu to be able to use them .. ( this will be the role to cuda/API and other library) .. if a software can take fully the advantage of it by use at the source this in account this will work.. but if not.. you will need manipulate the data for make this arm use it.. ( so i believe, the impact could be really limited in the situation Nvdiai have been able to put the developpers in a " no choice " situation ) .

If you are using Fortran C++ ... ARM cant work with that, it is needed the instructions you ask to him is coded in a language he can understand.. so you will need re encode them ( CUDA or i dont know how Nvidia will call it for this ) for be understand by it, before it can work with it ( and it can really work well, only if it can treat the data ) .. this is what HSA fundation is doing, create a new language who can be used by ARM and x86 cpu / and ARM based gpu ( Mali ) and x86 GPU ... what will do the maxwell ARM co processor outside use a langage create by Nvidia only. i dont know. Its too much proprietary at my sense to be usefull ( outside Nvidia and even then, they loose a lot of efficiency, as you will need encode this library again for be used by it ( the bigger problem of CUDA ).. this is going absolutely the other way the industry of semi conductor is going. ( ARM included ).. All the time you loose for use this library and API for get the results is again for a big part lost cause you need prepare them for it, and then if you need check them the work is again more long..

Last edited by lanek; 15-Dec-2012 at 19:02.
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