[Arun]

I know it is a bit early for this (ETA 2H13 on TSMC 20HP), but I figured this part of the forum hasn't been very active in the last few days, so might as well start it now rather than later.

We know the first (or one of the first) chips will include ARM-based Project Denver processor cores, but we don't know if the rest of the line-up will and so whether they will fundamentally be part of the programming model for next-gen CUDA. Some of the best info we have that *might* be about Project Denver is from Bill Dally's Echelon presentation, but that's aimed at a specific 2018 project which would imply it's talking about a 2015-2017 chip on 14nm or 10nm. And they've said it's clearly subject to change, so it's probably something mid-way between Maxwell and what they'll actually deliver for Echelon if they get the design win.

So yeah... speculation/expectations/random thoughts go here!

[OlegSH]

http://venturebeat.com/2011/02/01/mi...roject-denver/

MR: So we’ve been working on it for years(presumably on Denver). We’ve been in collaboration with ARM for a shorter time because it uses their future generation chip architecture. We’ve had hundreds of people working on it for a very long time. It’s been rumored to be everything, like an Intel-compatible product. We thought the best thing is to tell people what it was.

So it's not so new after all

[Megadrive1988]

So there's Kepler, Maxwell, Denver and Echelon.

[ahu]

In a related and confusing news, ARM doesn't have any immediate plans for 64-bit architecture:
http://www.xbitlabs.com/news/cpu/dis...hief_Exec.html

So, will Project Denver incorporate the first 64-bit ARM-core? I really can't imagine it being based on a 32-bit chip.

[entity279]

ARM has support for 40 bit addressing so the most immediate concern is alleviated.

What other major advantages are for a 64-bit ISA except full speed "double" operations? Now, out of those, how many of them would benefit a desktop CPU?

(I'm assuming that the first Denver iteration won't dream to target the traditional server market )

[ahu]

Well addressing single objects larger than 4 GB for instance. And are you suggesting that being forced to use paging methods would be OK from year 2014 onwards?

[Blazkowicz]

ARM is lowballing the issue as they are about to release a 32bit core and don't want it to look outdated ; that article basically said "we don't wish to talk about 64bit at that momen for market reasons".

remember Intel, they basically released the 64bit pentium 4 with the feature turned off and dealt with it as a little dirty secret.
maybe ARM wishes for the turnkey NAS for home and small business short term, where Atom with 1GB ram seems to dominate, but surely they need 64bit after that.

memory is amazingly cheap anyone can build a computer with 16GB well under 500 euros.

[ahu]

Agreed. And two more points:
- Fermi *already* has 64-bit addressing
- Maxwell and Project Denver are supposed to be used in supercomputers

So I would expect Maxwell ARM core to be at least 64-bit.

[entity279]

Originally Posted by ahu

And are you suggesting that being forced to use paging methods would be OK from year 2014 onwards?

If they're fast enough, why not? (TLBs FTW?). The compilers will generate the code, not you.

Of course, I do agree with you all that this is just a stop gap. It's just that I don't see it as a major issue as apparently you do; as long as nV uses this solution for the first iteration only and they will sell them (just) as co-processors in the high performance server markets.

Ninja-edit:

Actually I didn't have any big expectations about Denver when I first heard the announcement especially since ARM already announced 2-3 months ago that they don't see a large-scale ARM adoption in the server market (meaning: no, we don't have a 64 bit ISA planned). I personally view Denver as a sort of a first try from Nv. So in this context, only 32 bit ISA is no major drawback.

If I'm wrong however.. well then you're right . It's just that I fail too see how Nv could be that stupid to try to go against Xeons and Opterons with Maxwell

[mczak]

I am quite sure Project Denver is armv8, i.e. 64bit.
IMHO the last high-performance armv7 "mainstream" core will be cortex A15, slated for 2012. ARM might downplay 64bit now, but my interpretation of that xbitlabs quote is pretty much that they will move to 64bit after cortex A15.
But yes, this would likely make Maxwell one of the first armv8 chips out in the wild.

[Arun]

ARM did say NV licensed their next-generation ISA so that's definitively ARMv8 which is nearly certainly 64-bit. It's a good point that Maxwell might beat ARM to it though.

[rpg.314]

A speculation thread for a product whose predecessor is at least 6 months away

That's kinda jumping the gun, isn't it arun?

Anyways, the real question is what will be the level of integration of the cpu and gpu isa? Will nv expose gpu as a co-processor, sorta like 8086 and 8087, thereby integrating at the instruction stream level? That will be totally awesome, but would crucially depend on what kind of co-processor mechanisms arm will expose to it's licensees. BTW, does ARM allow making such extensions today to it's arch licensees? If not, then what is the mechanism that ARM allows for attaching accelerators?

The staid option is that the integration is restricted to LLC level and a driver controls scheduling of thread blocks.

[Blazkowicz]

I think more of the Cell ; for both the Cell or current and past designs for ARM licensees, you've got a general purpose core and an on-chip bus to talk to the rest of the chip. here the core seems pretty separated.
i.e., ARM sells a core typically to be integrated in a micro-controller or SoC. I guess that beyond the core (including maybe NEON) and its buses, what happens is no longer ARM's business. ARM cores talk to various DSPs, GPU and accelerators already and various kind of controllers and hardware.

I don't know anything about ARM and coherent links, shared memory or address space etc. though.

what made me think of the Cell is nvidia's emphasis on the memory hierarchy and memory locality. This is what tells apart Cell from classic CPUs, the local storage for the SPE.

[rpg.314]

Originally Posted by Blazkowicz

I think more of the Cell ; for both the Cell or current and past designs for ARM licensees, you've got a general purpose core and an on-chip bus to talk to the rest of the chip. here the core seems pretty separated.
i.e., ARM sells a core typically to be integrated in a micro-controller or SoC. I guess that beyond the core (including maybe NEON) and its buses, what happens is no longer ARM's business. ARM cores talk to various DSPs, GPU and accelerators already and various kind of controllers and hardware.

I don't know anything about ARM and coherent links, shared memory or address space etc. though.

what made me think of the Cell is nvidia's emphasis on the memory hierarchy and memory locality. This is what tells apart Cell from classic CPUs, the local storage for the SPE.

I'd like a larrabee-esque integration.

Once again, what kind/level of integration does arm allow in the name of coherent accelerators?

[ahu]

64-bit confirmed for Project Denver CPU

Preliminary silicon shown here:
http://www.brightsideofnews.com/news...licon-die.aspx

The FPU portion seems rather large to me.

[3dilettante]

I admit my curiousity made me click on that link.
Is it just me, or does the silicon underneath that overlay look a lot like a zoomed-in mismash of a GF100 die shot?

The silicon doesn't seem to match the description for things like the L1.

[Blazkowicz]

yes the areas feel labelled at random, and now I can see the symetrical features that cry "nvidia SP".
the colored rectangles are totally non-sensical.

this is an utterly stupid picture - and I fell for it

[rpg.314]

Originally Posted by 3dilettante

I admit my curiousity made me click on that link.
Is it just me, or does the silicon underneath that overlay look a lot like a zoomed-in mismash of a GF100 die shot?

The silicon doesn't seem to match the description for things like the L1.

And I thought they were putting up die shots of their first silicon.

[fellix]

Yes, the presented die shot is a patchwork from the official GF100 die photo... meh!

[DarthShader]

It's not even a "patchwork", it's a crop-resize-job from Fermi:



Just splash some random coloured rectangles over it, add some boundaries of functional parts...

[Tahir2]

So, NVIDIA gave that pic out? For a while I thought BSN created it.
Why would NVIDIA do that, isn't it outright outright deception?

[nutball]

Right.

I'm going to act the dumb blonde here.

I can see what's the cut/paste/rescale on the left-hand side of the pic, that it looks like a Fermi thing blah. Which is kind of what you might expect if they graft a Fermi thing onto another thing.

Where's the cut-and-paste of the right-hand side from Fermi stuff though??? Which bit of Fermi is that if the whole thing is fake?!

I realise that BSN is BS, that that article is 31% vitriol towards an unmentionable individual who is also a rumour-monger, blah blah, and so on. But I'm struggling to see the mapping from the right-hand-side of the upper supposed die-shot to the lower supposed die-shot, regardless of the dotted white lines.

?!

[Alexko]

Originally Posted by Tahir2

So, NVIDIA gave that pic out? For a while I thought BSN created it.
Why would NVIDIA do that, isn't it outright outright deception?

This puppy here is Denver!

[DarthShader]

Originally Posted by nutball

I can see what's the cut/paste/rescale on the left-hand side of the pic, that it looks like a Fermi thing blah. Which is kind of what you might expect if they graft a Fermi thing onto another thing.

Fermi shaders might be pretty potent, but I doubt 256 of them are able to emulate an ARM CPU, particulary the Load/Store and L1DCache on the left side.

Where's the cut-and-paste of the right-hand side from Fermi stuff though??? Which bit of Fermi is that if the whole thing is fake?!

It's indeed a bit harder to spt, since the right side is spammed with coloured rectangles. But if you look for standing out points in the shader groups on the Fermi die, you will be able to see them on the "Denver die" too, so it's another group of 4SMs, just like the left hand side.

[kyetech]

Sorry to bump an old thread.

But I was wondering what the speculation is for how many arm cores would be integrated into the Maxwell GPU?

Would they still be using the more traditional but updated stream (Fermi style) processors along side this?

If so whats the thinking on number of units stream processors needed to achieve the flops count quoted by nvidia.

Would the number of flops from the Arm cores be a significant contribution to the overall power of the GPU?