[fehu]

last time i eard about qdr was for a via chipset back in the k7 days

[rpg.314]

Originally Posted by iMacmatician

Bright Side of News: "Radeon HD 7000 Revealed: AMD to Mix GCN with VLIW4 & VLIW5 Architectures"

That's one bitching GPU. The memory bw is enormous. But is this the end of the road for GDDR5? For memory bw/pin in general?

[Alexko]

I don't think so. Chips at 7Gbps were announced a while ago, so they'll probably turn up eventually, but I think IHVs are put off by their power consumption for the moment.

Edit: and it's BS News, so there's a pretty good chance that it's BS indeed. Not that it doesn't sound credible, though.

[Ailuros]

Originally Posted by Alexko

Not that it doesn't sound credible, though.

So did the supposed former fake product line up that appeared a while ago; ironically if you take that table and replace XDR2 with GDDR5 it's give or take the same stuff as BSN claims.

[Dooby]

If those are the specs... holy moly. I have one of those please thank you very much. Infact, even though I've been saying I won't be getting a dual GPU card again (I have a 4870x2 atm) I would be inclined to wait around for the 7990. Jeeps. Annouce and release this card already!

[iMacmatician]

Originally Posted by Alexko

Edit: and it's BS News, so there's a pretty good chance that it's BS indeed. Not that it doesn't sound credible, though.

If it weren't for the "our sources…" stuff, I'd have thought it was a rumor roundup.

[TKK]

Originally Posted by Alexko

Not that it doesn't sound credible, though.

Basically I agree, but at least one part of the article is so wrong it hurts:

(read: Cape Verde becomes Lombok, Pitcairn becomes Thames etc.)

This part is funny, because it is pretty obvious from other leaks and driver entries that

Pitcairn = Wimbledon
Cape Verde = Heathrow & Chelsea
Lombok = Thames.

Especially the 'CV becomes Lombok' part made me laugh, didn't know Lombok was located in London


Another part I'm somewhat sceptical about is the 'all else is VLIW4' claim. Weren't the drivers indicating only a single additional VLIW 4 chip but 3 GCN chips?

I'm sure Lombok/Thames is VLIW, but I'm not entirely sold on CV and Pitcairn being VLIW4 just yet, although there are some reasons why this would make sense.

[UniversalTruth]

Bright Side of News: "Radeon HD 7000 Revealed: AMD to Mix GCN with VLIW4 & VLIW5 Architectures"

It's more like this:

Article: "Radeon HD 7000 Revealed: Bright Side of News to Mix Real Information with Fake One"

Originally Posted by TKK

...Weren't the drivers indicating only a single additional VLIW 4 chip but 3 GCN chips?...

Well, there is a make-up even for this, some people in their articles claim that those 3 chips are Tahiti XT, Tahiti Pro and New Zealand.

To laugh or to cry? Be aware!

[Alexko]

Originally Posted by TKK

Basically I agree, but at least one part of the article is so wrong it hurts:

This part is funny, because it is pretty obvious from other leaks and driver entries that

Pitcairn = Wimbledon
Cape Verde = Heathrow & Chelsea
Lombok = Thames.

Especially the 'CV becomes Lombok' part made me laugh, didn't know Lombok was located in London

Why do you have to be nit-picky about a few thousand miles?

Originally Posted by TKK

Another part I'm somewhat skeptical about is the 'all else is VLIW4' claim. Weren't the drivers indicating only a single additional VLIW 4 chip but 3 GCN chips?

I'm sure Lombok/Thames is VLIW, but I'm not entirely sold on CV and Pitcairn being VLIW4 just yet, although there are some reasons why this would make sense.

A good deal of the HD 7000 series might be renamed HD 6000 cards, maybe even a renamed HD 5000 one (bottom end, probably). That would explain there being a few VLIW5 models, but not VLIW4, as I don't think Cayman would be kept around.

[Ailuros]

Dumb question: what are the 64 ROPs good for if the supposed specs are real?

[3dilettante]

And why disable 4 of them when disabling 2 CUs? Past architctures and the GCN diagrams did not have a coupling of ROP count to SIMD/CU count. The primary linkage in the GCN pics was one between the pixel pipes and the L2 cache, which would scale based on the memory bus.

[no-X]

There are at least 3 or 4 double-confirmed configurations:

• 384bit GDDR5
• 256bit XDR2
• 384bit QDR DDR5
• 256bit 7Gbps GDDR5
• …

No EDRAM this time?

[Ailuros]

Originally Posted by no-X

There are at least 3 or 4 double-confirmed configurations:

• 384bit GDDR5
• 256bit XDR2
• 384bit QDR DDR5
• 256bit 7Gbps GDDR5
• …

No EDRAM this time?

How about it's a wee bit of everything and at the same time an elastic buswidth which can expand according to demands? What do you expect during pre-launch silly season anyway?

[LordEC911]

Originally Posted by Ailuros

Dumb question: what are the 64 ROPs good for if the supposed specs are real?

How exactly would you go from 32ROPs on a 256bit bus to 64ROPs on a 384bit bus?
Unless I missed something about the CU/ROP relationship.

[AlexV]

Originally Posted by Ailuros

Dumb question: what are the 64 ROPs good for if the supposed specs are real?

AUSUM Atomics. Because Andrew really needs them for his shadows.

[no-X]

Originally Posted by LordEC911

How exactly would you go from 32ROPs on a 256bit bus to 64ROPs on a 384bit bus?
Unless I missed something about the CU/ROP relationship.

Maybe ring-bus is back (I believe RV570 supported combination of 12 ROPs with 256bit interface)

[mczak]

Originally Posted by no-X

There are at least 3 or 4 double-confirmed configurations:

• 384bit GDDR5
• 256bit XDR2
• 384bit QDR DDR5
• 256bit 7Gbps GDDR5
• …

No EDRAM this time?

LOL.
btw 7gbps gddr5 has to be some kind of running joke, it is always "shipping early next year", since 2008 . Maybe it'll be true at some point...

[Ninjaprime]

Originally Posted by mczak

LOL.
btw 7gbps gddr5 has to be some kind of running joke, it is always "shipping early next year", since 2008 . Maybe it'll be true at some point...

I would guess its been around, just no one yet wants to make a 7 gbps capable memory controller. IIRC, AMD saying their transition from 4870 --> 5870 memory controller needed twice the logic/wiring, and similar reasoning for fermi's memory controller not being up to snuff with AMDs.

[Alexko]

Originally Posted by Ninjaprime

I would guess its been around, just no one yet wants to make a 7 gbps capable memory controller. IIRC, AMD saying their transition from 4870 --> 5870 memory controller needed twice the logic/wiring, and similar reasoning for fermi's memory controller not being up to snuff with AMDs.

Yeah, that and nobody wants the power consumption of 7Gbps chips either. That would be my guess, anyway.

[denev2004]

Originally Posted by no-X

There are at least 3 or 4 double-confirmed configurations:

• 384bit GDDR5
• 256bit XDR2
• 384bit QDR DDR5
• 256bit 7Gbps GDDR5
• …

No EDRAM this time?

Of course, eDRAM is mostly used to replace SRAM not DRAM.
It sounds so stupid if there are rumours about eDRAM

[no-X]

EDRAM is typically used as a bandwidth solution and as such it can be used as a replacement of high-speed wide-bus DRAM configuration (anyway it's not suitable for desktop).

[denev2004]

Originally Posted by no-X

EDRAM is typically used as a bandwidth solution and as such it can be used as a replacement of high-speed wide-bus DRAM configuration (anyway it's not suitable for desktop).

Really? I haven't heard any place where they use eDRAM instead of DRAM
I just know some chips prefer eDRAM against SRAM.

[Ailuros]

Originally Posted by LordEC911

How exactly would you go from 32ROPs on a 256bit bus to 64ROPs on a 384bit bus?
Unless I missed something about the CU/ROP relationship.

They should be de-coupled (if it's even remotely true which I severely doubt).

[3dilettante]

It's been used in consoles to reduce the need for a high-bandwidth DRAM bus, not DRAM itself.
A modest bus would still be needed to connect to the high capacity DRAM, at least until we learn how to stack scads of them on a 3d IC.

[mczak]

Originally Posted by Alexko

Yeah, that and nobody wants the power consumption of 7Gbps chips either. That would be my guess, anyway.

Well last time I checked the only offers even at 6gbps were factory overvolted (1.6V instead of 1.5V). If you read the announcements of those memory companies, you'd get the impression they had 7gbps chips running at 1.35V in 2009 which would certainly help with the power consumption. But of course those announcements are pretty shady - what they wanted to say is "we've got a chip which could maybe run at 7gbps at an undisclosed voltage (and we don't tell you how high it really needs to be because it isn't practically useful anyway) and the same chip can also run at 1.35V (but at half the data rate)"...
So if they could make 1.5V 7gbps chips they wouldn't require more power than what amd is currently using (at 1.6V).