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#101 |
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Senior Member
Join Date: Feb 2002
Posts: 1,865
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arjan makes good poionts above. Longer bursts provide much higher bus utilization. Unless you only rarely use contigous data, longer bursts are usually a good idea, from a bus efficiency point of view.
For less technical readers, I'd like to point out there is a problem that kicks in earlier than passing the point of optimum bus utilization. Caches. Bursting in extra data is very cheap in terms of bus cycles in and of itself, but it is expensive in that you end up using a larger portion of your caches for storing data nobody wanted. Furthermore, the data that is replaced has to be written back to memory, which costs bus-cycles. Thus, the break-even point for memory bus read burst length is much shorter in "real life" than what would be apparent from only looking at protocol efficiency, because longer bursts also lower cache efficiency and increases cache logic demands on bus cycles. The trade-off is clearly application and GPU architecture dependent. It is obviously impossible for an interested bystander like me to say what would be an optimum. I would predict that it isn't terribly sharp though, in other words that the finer points only make small differences Edit: Small addendum. You can increase cache efficiency by tagging data that you know shouldn't be cached, or by manually locking and releasing data in the cache. Would be workeable in for driver writers. Entropy |
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#102 | |
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Senior Member
Join Date: Feb 2002
Posts: 1,865
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Quote:
"It's more of a way to get rather high bandwidth out of cheap components...." Now if that doesn't sound pretty damn useful, I have understood nothing about the biz. The biz is also conservative though. I thought that 256-bit buses would come before any new memory technology, and that turned out to be a correct guess. But I most certainly wouldn't rule QBM out completely. If I were to build a card that needed a lot of memory with a lot of bandwidth, i.e. the memory would need to be big and fast, I would definitely look into QBM. And maybe reject it. But maybe not, since it most obviously _would_ be useful for such an application, not better than going 128 -> 256 bit wide perhaps, but quite possibly more appealing than going 256 -> 512. Plus, it makes for a nice technological cycle. 64-bit SDR -> 128-bit SDR -> 128-bit DDR -> 256-bit DDR -> 256-bit QBM (Too bad the QDR name was appropriated for memory technology which doesn't fit the technological pattern.) There are several alternatives to the last step in the pattern above, but I wouldn't bet on cheap bandwidth going out of fashion all that soon. IF it is cheap enough, and not too difficult to incorporate into the design compared to alternative approaches, it may well be used. In this forum, it seems that many are of the opininion that 128-bit DDR at 200+ MHz is some kind of high-end interface today. It's not. It is used on sub-$60 cards for crissakes. What has been limiting new memory approaches is that they have to fit a very tight pricing envelope for a manufacturer to sell a design in the volume segment. DDR didn't quite fit there when it came, but soon did. The same for 256-bit buses now. The next step is up for grabs. But CHEAP is at the very top of the list for importance. Entropy |
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#103 | |
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Senior Member
Join Date: Feb 2002
Location: Brasil
Posts: 1,790
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Quote:
Looks like LMA do always a burst 2. If you need a texture then the LMA do a 256bits read (burst 2). Now it will have to do a 512bits read (128bits burst 4), or maybe do a 256bits texture read + 256 framebuffer read. I hope you are right and that the protocol eficiency improvment will be enough to compensate the longer burst delay. |
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#104 | |
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B3D Shockwave Rider
Join Date: Feb 2002
Posts: 1,803
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A rumour that Microsoft will build their own chips for the X-Box 2.
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As far as the license fees is concerned, I have no idea if they could charge companies like Nvidia for the technology. |
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#105 |
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Junior Member
Join Date: May 2002
Posts: 42
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I see MS taking more control over the design and production of XBox2 compared to XBox1 as a very likely step. With the current involvement of Intel and NVidia it will be very hard for MS to compete with Sony price-wise. The selection of Intel and NVidia was a logical step at the time to get XBox out without delays. But a combination of licensed MIPS- (or possibly an x86-) and Gigapixel-cores, where MS was responsible for the actual production would have been a better long-term solution.
This time, with XBox2, MS may have the time to develop the system in-house. I do believe they will try to get it out on the market before PS3, which could mean we will see it as soon as Christmas 2004. The design could be well underway, making 2004 a possibility. MS do have a lot of in-house experience in 3D graphics, and with their deep pockets they can basically "hire the experience" they are missing. Not sure about the CPU design though..... They could of course license complete cores instead of creating their own architectures. MIPS? PowerVR? Bitboys XBA (don't laugh)? Not sure how important backward compatibility with XBox1 is. But I guess they will learn from the PS->PS2 transition that it's not that important (or is it?). |
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#106 | |
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B3D Shockwave Rider
Join Date: Feb 2002
Posts: 1,803
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Quote:
If Bit Boys got in on the X-Box 2 action, that would be so entertaining. Not as amusing if Microsoft used Suns MAJC CPU though I think backward compatibility is a good thing overall. |
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#107 | |
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Junior Member
Join Date: Feb 2002
Location: Wales
Posts: 15
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