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#51 | |
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#52 |
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Well ben, a 128bit bus would have to be operating at 3Ghz for 50GB/s of bandwidth. That aint gonan happen, you need at least a 256 bit wide bus but then you are still talking 750Mhz/1.5ghz DDR memory. 325Mhz QDR with a 256bit wide bus would manage that, the expense would be rediculopus though. Wider busses increases the minimum amount of memory chips you can have too which will also drive up expense.
Dave |
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#53 |
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Regular
Join Date: Feb 2002
Posts: 5,951
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Ain't gonna happen? Price will be ridiculous? Don't underestimate the mother of invention: necessity.
Think back about 5 years ago, as ben was saying. At the time, the best single chip solution, bandwidth wise, was the Riva 128. 128 bit, 100 Mhz, SDRAM. Approx 1.6 GByte/sec. Now, if five years ago, I told you we would have 10 GB/sec by 2002, you would probably answer the same way you are now: ain't gonna happen...too expensive...to complex. All the same arguments about complexity, chip density, traces, etc. you make now would have applied then too. The "impossibility" of affordable raw bandwidth is what the PowerVR / Deferred rendering camp was pretty much counting on to bolster the future of the bandwith saving technology. Raw bandwidth simply would not be remotely affordable to keep up with GPU demand. But don't feel bad. There weren't too many people 5 years ago (myself included) that probably though 10 GB/sec with "conventional external ram" would be a reality today. But here we are, 5 years later sitting on 10 GB/SEc, and reportedly on the virge of 20 GB/sec. 50+ GB/sec in another 4-5 years time? I wouldn't be surprised at all. That's not to say I think it will be an easy road, but it seems that every time we think we've hit a "bandwidth wall" the past 5 years, IHVs have found some way through it. |
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#54 | ||||||||
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4 years ago 2.75gb/s was the highend video bandwidth, today its 10.15gb/s with DDR, around 8gb/s effective since DDR is less efficient then SDR. Theoretically bandwidth for the highend has increased by 3.7 times in the last 4 years, meaning 37.5gb/s for highend ram in 2006. Effectively its increased by about 2.9 times when factoring in the fact that DDR is not actually twice as fast as SDR. I think 30-35gb/s is a decent guess for 2006. 50gb/s sounds over the top to me and frankly 70gb/s is insane IMO Quote:
However as I've said I don't even agree with 50gb/s video ram in 2006. Even if I did the cost factor is still their as we're talking about XBox 2 using highend cutting edge 50gb/s ram (that I don't even think will excist Quote:
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I suppose in 5 years 50GB/s could be possible as highend cutting edge video ram (more like 40gb/s thought IMO), but certainly not in 4 years or even less IMO. Were most likely looking at 35GB/s at the start of 2006 IMO... maybe 40GB at most at the very top end. |
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#55 |
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If bandwith was not an issue we would have perfect quality edge anti-aliasing, developers wouldnt need to worry about structuring everything right to hit the caches ... etc etc.
Just because the hardware and software is adapted to deal with the available bandwith does not mean we would not be in a far better position with more of it right now. |
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#56 | |
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Itchy
Join Date: Feb 2002
Location: United Queendom
Posts: 2,858
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Necessity X Cost / Technological Feasible Level = Real World Specs(RWS) rather than Peak Performance Specs(PPS) :P |
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#57 | |
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Regular
Join Date: Feb 2002
Posts: 5,951
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I didn't say bandwidth wasn't an issue. Nor did I say we wouldn't be in a better position if we had a part that used it more "efficiently". I've been begging for someone *cough, PowerVR, cough* to build a deferred renderer that utilized the latest memory available for what, 5 years now?
I am only stating that many seem to paint a "bleak" picture for available raw bandwidth for the future. They have been painting this picture for the past 5 years, making the argument for architectures like deferred rendering sound more like a "necessity" than an "improvement" when advancing graphics performance. At this point, one has to start questioning if the bandwidth "wall" will actually happen, rather than assume it will happen in the near future. Quote:
http://www.anandtech.com/showdoc.html?i=65 Riva128 was using, 128 bit, 100 Mhz S(D/G)RAM. And actually, although the original TNT core was clocked at 90 Mhz, The ram was clocked at 110. Be careful when you nit-pick! |
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#58 |
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I dont know "they" so I cant speak for them. The bandwith "wall" never went anywhere, its always been a bottleneck and will be for a while yet.
The success or failure of given specific chips prooves nothing but their individual quality, you can try to extrapolate that to the quality of the underlying principles of the architectures ... but in the end your extrapolation is no more rooted than my speculation IMO :) Cant proove the negative and all that. |
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#59 | |
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Regular
Join Date: Feb 2002
Posts: 5,951
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That's not saying that bandwidth isn't a problem now. Of course it's a bottleneck. But the point is, the situation doesn't seem to be getting progressively worse with each generation of product. (That was the thought 5 years ago.) "Effective Bandwidth" has kept up with increasing demand from GPUs. It kinda reminds me of Moore's law. No one claims that transistor density isn't a "problem." That's the bottleneck for more powerful processors. And every year it seems there's a new "wall" placed on fabrication processes. "After XXX microns, we'll be hitting a wall and will need some new radical approach to increase transistor density". And it seems every year that point gets pushed further away as new evolutionary ways are discovered and implemented. |
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#60 |
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Itchy
Join Date: Feb 2002
Location: United Queendom
Posts: 2,858
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I stand corrected Mfa
... my bad Since this is 3D Hardware and not just related to Consoles on the PC side I think the AGP bus is fast becoming the next hurdle. |
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#61 |
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SNAKES... ON A PLANE
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High-end five years ago was Voodoo2 with three 64-bit 100MHz EDO DRAM channels... that's 2.4GB/sec.
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For Great Justice Move Every 'Zig' |
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#62 | ||
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Join Date: Apr 2002
Posts: 2,158
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Remember 'Termite Games' - I think a programmer from their used to post here. Their DVA engine, back a year or 2 ago... may have changed, comes to mind because it used a basic CPU and some agressive visability and culling to show onscreen polygon counts and dynamic lighting way ahead of it's time. Nobody's designing for a fully software drived 3D pipe, yet... So comparing games with 'software' support is just wrong. Do you not read my posts? I don't even think they're will be fragment shading in 5 years, so wheres the problem? Sonys backing the Stanford based, Real-Time High Level programmable Shading project... my guess is they're doing that for a reason. Besides, if your drawing a 80,000 polygon mesh/character, whats wrong with shading at a per vertex level? When the size of the average polygon nears that of a pixel, your almighty hardware rasterizer breaks down [Without massive design philosophy changes] and you can achieve sub-pixel accuracy with vertex shading. http://www.itworld.com/Comp/1437/itw...-12_supercomp/ PS. CELL looks to be low-k di-electric, CU interconnects, SOI on a sub-0.1um. The 0.10um SOI that was liecensed was later stated to be the processed used in the combined Emotion Engine-GS chip. |
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#63 | |
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Join Date: Apr 2002
Posts: 2,158
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#64 | ||||||||
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ea_spouse is H4WT!
Join Date: Feb 2002
Location: 53:4F:4E:59
Posts: 1,586
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You're also contradicting yourself a bit by extolling the virtues of a "fully" programmable GPU vs. a software rasterizer (assuming you're talking about total rasterization and not just setup), since code running utilizing a "fully programmable" GPU is essentially a software rasterizer in itself (excepting certain fixed-functions like setup). Quote:
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Of course I won't get into whether Sony/Toshiba/IBM (STI? EDIT: I see Vince responded in better detail... |
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#65 | ||
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Join Date: Feb 2002
Posts: 5,951
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Third, if you are going to say that, we might was well doble that to six 64 bit 90 Mhz modules (4.8 GB/sec), due to V2 SLI. Most importantly though, I'll repeat with emphasis: Quote:
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#66 |
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My point was that you are already take it as fact that the potential performance differential for alternative architectures has stayed the same over the years ... the fact that the few companies left are sticking to them makes the assumption reasonable, but it doesnt proove anything.
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#67 |
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Itchy
Join Date: Feb 2002
Location: United Queendom
Posts: 2,858
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Speaking in pure MHz terms... fatest accelerators now use 300MHz DDR (equivalent of 600MHz)... and GPU's have increased clockspeed from xx amount to 300MHz+
Memory tech has improved dramatically, people are just saying they want/need more bandwidth right now and probably forever.... Dave Perry said something about developers being a lot like gas...gas fills whatever volume it is in [or something like that]...and still wants to push out 8)
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Time is an illusion. Lunchtime doubly so - Douglas Adams |
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#68 | ||
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ea_spouse is H4WT!
Join Date: Feb 2002
Location: 53:4F:4E:59
Posts: 1,586
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All things being equal, given the choice of 300MHz DDR-RAM and 600MHz SDR-RAM, I'd take the later in a heartbeat even though they both provide the same theoretical bandwidth. |
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#69 | |
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B3D Shockwave Rider
Join Date: Feb 2002
Posts: 1,810
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http://ne.nikkeibp.co.jp/english/200...iv/int5_1.html |
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#70 |
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Senior Member
Join Date: Feb 2002
Posts: 3,267
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Thanks Brimstone,
MFA, that's where I hear it, from Kutaragi himself. |
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#71 | |
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Member
Join Date: Feb 2002
Location: Seattle, WA
Posts: 124
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Higher Order Surfaces turned out to be difficult to author, difficult to control, slow to render on current hardware, not very bandwidth efficient at low levels of detail, and not implemented uniformly across different hardware architectures. On the other hand, triangle meshes are easy to author and use, only take up twice as much space at low levels of detail, and render really quickly on all modern hardware. HOS isn't even used very much as a non-real-time data compression technique. Quake 3 uses them a little, and I think Jax and Daxster has an ellipsoid primitive, but most games don't bother. This is because just about all you can do with HOS is make smoothly curving surfaces, which aren't that common in video games. (Most landscapes and architecture aren't smooth, and most parts of most monsters / players aren't smooth either.) I think per-pixel displacement maps on top of normal polygons will become common in the future, but I'm not sure when we'll see traditional HOS (either NVIDIA's nurbs or ATI's smothed meshes) used very much. |
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#72 |
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EE? GS?
Somebody? |
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#73 | ||
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B3D Shockwave Rider
Join Date: Feb 2002
Posts: 1,810
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#74 |
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Ah, well I still say he's off his rocker ... the main problems to be solved with large scale distributed systems are algorithmic and its way too early to limit yourself by trying to pour it into hardware. Waste of time since the networks themselves dont exist, cant exist even without cheap fibre speed photonic switching.
Mr. Kutaragi still see's Cell as a computation node though ... not a pure communication one, so the EE/Cell seperation does not make a whole lot of sense if you want to take his interview at face value. Personally I think its a bit of hocus pocus to confuse the competition, I doubt they are spending all that money to make an architecture which only makes sense for supercomputers which can lay a fibre backbone. |
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Join Date: Feb 2002
Posts: 823
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DaveB-
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'01 300MHZ DDR 8.49GB/sec '06 900MHZ QDR 53.64GB/sec That's if we stick to a 128bit bus. Darren- Quote:
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KyroII has good OpenGL drivers? They must have improved a staggering amount since I had one. Quote:
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So you chew up a load of processing power on geometry, and then chew up more on a geometric LOD system, then chew up some bandwith along with more CPU overhead to utilize an alternating vertex shader scheme based on distance tied in with your LOD system, then amplify your T&L load significantly by relying on extremely complex vertex shader routines, which you will need to have six or more of at least to avoid serious aliasing issues. Building for the code for all that will be real simple though, right? Particularly using a completely new architecture with a new instruction set to learn, new register architecture and primitive compilers on top of having massive multi threading issues to work around. Quote:
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