[Gipsel]

Originally Posted by AlexV

Yes.

I don't know. The front wafer looks very much as it would contain a six core CPU, albeit not in 32 or 28nm (i.e. it may be just a 45nm Thuban wafer, I'm too lazy to check the die size).

If we assume for a moment the front wafer is 45nm SOI, the middle wafer a 32nm SOI and the last one a 28nm bulk (with some test structures on it) and consider that on the middle wafer one can recognize a large cache structure (L3?) accompanied by 4 smaller blocks (with smaller caches), it could even be a 4 module Bulldozer die if it would have been taped out and did already the first run through the fab when the photo was taken

[no-X]

According to the old BSN article:

"Global Foundries representatives would not talk about what chips were on that wafer, but they were definitely not the test SRAM structures that we saw in June."

[AlexV]

Originally Posted by no-X

According to the old BSN article:

"Global Foundries representatives would not talk about what chips were on that wafer, but they were definitely not the test SRAM structures that we saw in June."

Ugh, BSN wouldn't know the difference between a more complicated test structure and a pubic hair even if it was explained to them by all of Intel's process engineers. Also, there is more to test structures than SRAM, so the fact that a rep purportedly said that those aren't the same SRAM test structures is hardly equivalent to there being some bombad new secret chips on those wafers, or even equivalent to saying that there's a working chip in there as opposed to all sorts of functional units routed and placed.

On another note, shouldn't we wait for GF to actually deliver anything before we jump up and down with joy over ATI making chips there? As far as I can see they're still a ways off from proving their viability as anything but AMD's foundry.

[AlexV]

Originally Posted by Gipsel

it could even be a 4 module Bulldozer die if it would have been taped out and did already the first run through the fab when the photo was taken

Considering when BD actually taped out, that would have required a jiggawatt of power very close to the present day being used, and we've measured no such surge in power consumption recently

[rpg.314]

Originally Posted by AlexV

Ugh, BSN wouldn't know the difference between a more complicated test structure and a pubic hair even if it was explained to them by all of Intel's process engineers.

[caveman-jim]

Originally Posted by AlexV

Ugh, BSN wouldn't know the difference between a more complicated test structure and a pubic hair even if it was explained to them by all of Intel's process engineers. Also, there is more to test structures than SRAM, so the fact that a rep purportedly said that those aren't the same SRAM test structures is hardly equivalent to there being some bombad new secret chips on those wafers, or even equivalent to saying that there's a working chip in there as opposed to all sorts of functional units routed and placed.

On another note, shouldn't we wait for GF to actually deliver anything before we jump up and down with joy over ATI making chips there? As far as I can see they're still a ways off from proving their viability as anything but AMD's foundry.

THOSE ARE NEW ATI GRAPHICS PROCESSORS AND STOP MAKING FUN OF MY FRIEND IT IS TOO A NEW GPU FROM ATI AT GF AND ITS COMING OUT NEXT MONTH!


omg, haxxorz.



Also, Dual 40nm GPU next generation ATI card this year:

http://www.fudzilla.com/graphics/gra...comes-from-ati

We've just learned that ATI's next generation, let's call it Radeon 6000 series, is going to get a new high-end card. We are talking about a dual-chip card based on new 40nm chips that are expected to get slightly faster than the current generation. The best part is that it comes in 2010.

We see the new performance chips as a tweaked version of the highly succesful Cypress core, but this time they will introduce support for the new HDMI interface as well as new UVD – Eyefinity. Eyefinity will become more functional and cheaper to implement on multiple monitor setups.

Of course the core itself will be slightly improved, but we don’t expect a spectacular performance increase. It will be faster than the current generation, that much is clear, but we still don't know much about Nvidia's answer to this card.

Meh, same old same old...

I keep coming back to thinking about AMD's year on year progression of performance per watt. Keeping loosely to 'Moores Law' then next generation on 40nm will have to offer more performance for less power consumption. Performance of theoretical single precision TFLOP's, that is.

It's certainly possible to use 40nm process at TSMC better, is it possible to increase SP count without changing SP design, with better power consumption? Tall order to hit that perf/watt plot.

I'm ready to be surprised though (no, not like that, put your pants back on).

[no-X]

Found it. The GF person, who talked to BSN, probably missinformed them, because the waffers really aren't 28nm. Gipsel is right. Only the yellow wafer is 28nm (bulk, SRAM), the second one is 32nm (SOI) and the last one is 45nm (SOI, Thuban - or at that time called "45nm Istanbul").

I think it's quite likely, that the 32nm SOI product was Fusion. It isn't any 28nm GPU, definitely, so fudzilla is right, that we couldn't see any 28nm bulk wafer yet...

[Squilliam]

Would it make sense to stitch two Juniper class GPUs onto the same package ala the old Core 2 Quads from Intel? Sure the package would cost more but they could easily make up for that in only having to design one chip, not two and higher yields given they could span the Juniper level chip over 4 product classes:

67xx, 68xx and 69xx.

That way the perfect dies could all become 6870 and 69xx class chips, the dies which meet the leakage requirements but have a defect could become 6850, the dies which are higher leakage without defects could become 6770 dies and the ones which are defective and high leakage could become 6750 dies.

[rpg.314]

Originally Posted by Squilliam

Would it make sense to stitch two Juniper class GPUs onto the same package ala the old Core 2 Quads from Intel?

No. Setup/rasterization is a hard serialization/choke point. And even an MCM will be like multi gpu sli/crossfire of today.

CPU's can scale with MCM's because they don't have any such problems to worry about.

[Squilliam]

Originally Posted by rpg.314

No. Setup/rasterization is a hard serialization/choke point. And even an MCM will be like multi gpu sli/crossfire of today.

CPU's can scale with MCM's because they don't have any such problems to worry about.

What about the side port?

We had first generation sideport RV770.

Second generation sideport was scrapped, but obviously development continued even if the current chips don't feature it.

Third generation side port? What would that be able to do?

[rpg.314]

Originally Posted by Squilliam

What about the side port?

We had first generation sideport RV770.

Second generation sideport was scrapped, but obviously development continued even if the current chips don't feature it.

Third generation side port? What would that be able to do?

I have no idea if side port can fix it. But i/o pins are expensive as they are relatively scarce on smaller dies.

[Squilliam]

Originally Posted by rpg.314

I have no idea if side port can fix it. But i/o pins are expensive as they are relatively scarce on smaller dies.

Well they are expensive, but given the short distance between the two dies they could potentially have a lot of throughput and relatively low latency on only a small number of pins.

Realistically how much data would have to be shared in order to make a pair of GPUs perform close to how a single larger die would?

[rpg.314]

Originally Posted by Squilliam

Well they are expensive, but given the short distance between the two dies they could potentially have a lot of throughput and relatively low latency on only a small number of pins.

True, but another question is whether you'd be better off using those I/O pins for memory? Especially with memory bandwidth growth slowing/stalled.

Realistically how much data would have to be shared in order to make a pair of GPUs perform close to how a single larger die would?

Potentially, all the geometry data. And mind you it isn't small with all the tessellation.

[rpg.314]

http://www.phoronix.com/scan.php?pag...green_3d&num=1

AMD's Radeon HD 6000 series whose GPU family codename is "Southern Islands" is launching later this year. Besides their open-source developers starting early on this Linux upbringing (their proprietary driver team still should have same-day Linux support), it's rumored that the ATI Radeon HD 6000 architectural changes aren't too significant, which should reduce the workload of the open-source developers by being able to build upon the existing DRM/Mesa/DDX code.

Better linux drivers, .

Is some ocl love on the table too, or not?

[GZ007]

Originally Posted by rpg.314

Potentially, all the geometry data. And mind you it isn't small with all the tessellation.

And what if the two dies wouldnt be same . One would have rops, cache, memory controlers, IO and the second one rest (and maybe separated they could have smaler die are together if they would be clever placed ). The second die would be only conected to the first die and not the pcb. You dont need to share anything this way just lots of bandwith and low latency between the two.

[rpg.314]

Originally Posted by GZ007

And what if the two dies wouldnt be same . One would have rops, cache, memory controlers, IO and the second one rest (and maybe separated they could have smaler die are together if they would be clever placed ). The second die would be only conected to the first die and not the pcb. You dont need to share anything this way just lots of bandwith and low latency between the two.

Correct me if I am wrong, but what you just described, isn't it a fancy layout which does not enjoy the advantages of lower development costs? A bit like x360's gpu.

[trinibwoy]

Originally Posted by GZ007

You dont need to share anything this way just lots of bandwith and low latency between the two.

You will never be able to achieve the levels of on-die bandwidth and latency available today by connecting two separate die together.

[GZ007]

Originally Posted by trinibwoy

You will never be able to achieve the levels of on-die bandwidth and latency available today by connecting two separate die together.

The mind blowing xTB/s on-die bandwith is agregated bandwith of the cache-s thanks to the paralel rendering. The main idea was to not split the shader clusters and leave them on the second die.
Do you think that the xenos parent die has just 32GB/s on-die bandwith because the two dies
have only 32GB/s bandwith betwen them.

[trinibwoy]

Originally Posted by GZ007

The mind blowing xTB/s on-die bandwith is agregated bandwith of the cache-s thanks to the paralel rendering. The main idea was to not split the shader clusters and leave them on the second die.
Do you think that the xenos parent die has just 32GB/s on-die bandwith because the two dies
have only 32GB/s bandwith betwen them.

Uh what? There's 32GB/s between the dies but there's also 256GB/s between the ROPs and memory on the eDRAM die which only serves framebuffer operations. Texture, geometry and all other data is stored on regular old DDR3 connected directly to the main die. Your analogy doesn't work as Xenos is a highly customized setup not suited for the general workloads a desktop graphics card must handle.

In your design how are you planning to expose the full DDR bandwidth to the shader core and texture units?

[Squilliam]

Originally Posted by rpg.314

True, but another question is whether you'd be better off using those I/O pins for memory? Especially with memory bandwidth growth slowing/stalled.

But don't you need something like 64 pins for a 32bit bus? 64 pins isn't going to make much difference, especially as ATI doesn't seem to use 96/192/384 bit bus widths.

Potentially, all the geometry data. And mind you it isn't small with all the tessellation.

Which would surely not be too excessive given the PCI-E isn't significant in comparison?

[hoom]

Could have sworn we went through this multi-die stuff both of the last two generations & it still hasn't happened

[Jawed]

Precisely. Maybe at some point they'll ditch the bridge chip.

[rpg.314]

Originally Posted by Squilliam

But don't you need something like 64 pins for a 32bit bus? 64 pins isn't going to make much difference, especially as ATI doesn't seem to use 96/192/384 bit bus widths.

I don't think 64 pins come cheap, especially on juniper class die.

Which would surely not be too excessive given the PCI-E isn't significant in comparison?

Data is sent across pci-e once, but read from gpu ram many times. Even if upload-to-gpu is slow, it has less impact on performance than gpu bandwidth.

[Unknown Soldier]

ATI Preps New Dual-Chip Flagship Graphics Card - Rumours

ATI, graphics business unit of Advanced Micro Devices, will launch a new dual-chip graphics card by the end of the year, according to a rumour published by a China-language web-site. The card will replace the current top-of-the-line ATI Radeon HD 5970 graphics accelerator.

The forthcoming flagship graphics board will be powered by two chips featuring the yet unannounced Southern Islands architecture. The information indirectly implies that power consumption of the future graphics processing units (GPUs) will not be too high and will allow AMD's ATI unit to put two of such chips onto a single card without exceeding standard 300W power envelope, which is crucial for meeting requirements of large system builders. As reported previously, ATI Radeon HD 6000-series graphics boards will become available in late October or early November, 2010.

Not a lot is known about the Southern Islands family of products. The SI family will offer higher performance compared to currently available ATI Radeon HD 5000 “Evergreen” line, but will hardly be considerably more advanced in terms of feature-set. It is rumoured that designers of the new GPUs concentrated mostly on improving efficiency, but not on building something completely new from scratch, which is why certain building blocks of the new Sothern Islands family will be inherited from the current Evergreen line.

According to the report from Cnbeta web-site, ATI "Southern Islands" will also feature an improved version of ATI Eyefinity technology as well as a more advanced Universal Video Decoder (UVD). The improvements will allow the new chip(s) to playback video in ultra high definition (UHD) resolutions. Unfortunately, at present there are no commercial UHD movies, hence, a more important feature of future GPUs will be ability to upconvert full-HD Blu-ray movies to higher resolutions.

ATI/AMD did not comment on the news-story.

News Source: http://www.xbitlabs.com/news/video/d...d_Rumours.html

I know they talking efficiency but how much better will 6xxx series Tessellation be? Anyone care to guess. As far as I know, that was the low point the 5xxx series had vs the G100. Also, how would ATI go about making it better than the G100?

[rpg.314]

This launch cycle seems to be mirroring the evergreen launch so far.