[Lightman]

Originally Posted by 3dilettante

The clock appears too high to be for idle, if CnQ is on.
I would hope that is not max turbo, given that the design has done so much to slim things down to allow for clock scaling.

Well, on one hand I would like to agree with you and hope this is full load on on all cores clock, but one another hand I realize this is 8 core CPU. Also by AMD's tradition early CPU samples are clocked conservatively by default.

[Blazkowicz]

I've checked for IOMMU on the chipsets, and found out it's available on all variants , according to unambiguously wording of some pieces of news.

this with the backwards compatibilty means I can upgrade from AM2 and 2GB ddr2 to AM3+ and 4GB ddr3 while keeping the same CPU, and game under virtualized windows 7, eliminating the need for dual boot.
good news, a 890FX or 990FX board would cost me as much as CPU, graphics card and memory combined.

[gongo]

What this means....new news is good news! Waiting to upgrade to 6 cores Gulftown..or Bulldozer....quads are old skool.

http://www.eetimes.com/electronics-n...z?pageNumber=2

Rick Merritt
2/21/2011 7:30 PM EST
AMD Bulldozer, Intel server CPUs

Advanced Micro Devices provided more details on its new Bulldozer core first described at Hot Chips in August. AMD senior engineer Hugh MacIntyre said the core enables 3.5 GHz performance is same power and thermal envelope as AMD's prior core design.

The core delivers linear performance across a range of frequencies and 0.8-1.3V voltages it will need to operate. It uses 213 million transistors in a 30.9mm2 block with 11 metal gates in a 32nm SOI process, he said.

A separate paper described Bulldozer's 40-entry instruction out-of-order scheduler and execution unit that can issue up to four instructions per cycle. The unit helps the core meet its target of delivering 90 percent of performance of past AMD cores with a significant reduction in area and power, said Michael Golden, another AMD engineer.

[3dilettante]

A separate paper described Bulldozer's 40-entry instruction out-of-order scheduler and execution unit that can issue up to four instructions per cycle. The unit helps the core meet its target of delivering 90 percent of performance of past AMD cores with a significant reduction in area and power, said Michael Golden, another AMD engineer.

This sounds like a miswording or a misquote.
The targets for Bulldozer's core were not set at 90% of earlier cores, it was supposed to be higher-performance.

[Mize]

Originally Posted by 3dilettante

This sounds like a miswording or a misquote.
The targets for Bulldozer's core were not set at 90% of earlier cores, it was supposed to be higher-performance.

Ugh.

So the AMD quote of 50% faster than a 950 at lower clock...hmmm...
950: 4 cores x 1 = 4

BD: 8 cores x .9 x .8 (~20% slower per clock on Phenom II) = 5.76

Please say no!

[DarthShader]

That guy got it wrong. It should be more like:

As Michael Golden, an AMD engineer, explained during its presentation, each dual-core module, when fully loaded, is capable of delivering 90% of the speed of a similar native dual-core processor, while featuring a lower power consumption and utilizing less die space.

http://news.softpedia.com/news/AMD-T...1-185657.shtml

Which is known for about half a year now.

[3dcgi]

Originally Posted by 3dilettante

This sounds like a miswording or a misquote.
The targets for Bulldozer's core were not set at 90% of earlier cores, it was supposed to be higher-performance.

It could be a misplaced quote about Bobcat.

[jakobx]

I thought it meant that running two cores in one module achieves 90% of the performance compared to running only one core in a module. I could be completely wrong

[Triskaine]

Originally Posted by jakobx

I thought it meant that running two cores in one module achieves 90% of the performance compared to running only one core in a module. I could be completely wrong

You are right. Mister Golden was simply misquoted, here's what he said originaly:

"...As Michael Golden, an AMD engineer, explained during its presentation, each dual-core module, when fully loaded, is capable of delivering 90% of the speed of a similar native dual-core processor, while featuring a lower power consumption and utilizing less die space.
This enables AMD to pack more cores inside the same die space and power budget..."

[hoom]

There are a bunch of new blog posts regarding ISSCC presentations, doesn't seem to be anything much in the way of detail there though
http://blogs.amd.com/work/2011/02/18...at-isscc-2011/
http://blogs.amd.com/work/2011/02/21...ign-solutions/
http://blogs.amd.com/work/2011/02/21...hats-in-a-box/
http://blogs.amd.com/work/2011/02/22...gy-efficiency/
http://blogs.amd.com/work/2011/02/23...the-cool-kids/

There is a link in one of them to the Hotchips presentation which I haven't seen before & does include nice detail though
http://www.hotchips.org/uploads/arch...-Bulldozer.pdf

[itsmydamnation]

Originally Posted by hoom

There are a bunch of new blog posts regarding ISSCC presentations, doesn't seem to be anything much in the way of detail there though
http://blogs.amd.com/work/2011/02/18...at-isscc-2011/
http://blogs.amd.com/work/2011/02/21...ign-solutions/
http://blogs.amd.com/work/2011/02/21...hats-in-a-box/
http://blogs.amd.com/work/2011/02/22...gy-efficiency/
http://blogs.amd.com/work/2011/02/23...the-cool-kids/

There is a link in one of them to the Hotchips presentation which I haven't seen before & does include nice detail though
http://www.hotchips.org/uploads/arch...-Bulldozer.pdf

here is the hot chips presentation video
http://www.hotchips.org/archives/hc2.../session7.html

[hoom]

Oh cool thanks

[fellix]

Pretty much "undoctored" die-shot me thinks. Very modular design... too much, if you ask me.

[Npl]

whats to the left of the northbridge (across the crossbar)? Seems way to big to be simple filler space or traces. Could almost fit another 2MB cache there

[fellix]

You can see a lot of such "empty" space on the six-core Phenom die. Just traces, what it looks like.

[Blazkowicz]

lots of breathing room
also, cut in half and imagine a next-gen GPU on the left side.

[Triskaine]

Originally Posted by Blazkowicz

Also, cut in half and imagine a next-gen GPU on the left side.

That's what Trinity will be in 2012.

[fellix]

Leaked benchmarks of Interlagos in F@H:

F@H Benchmarks Interlagos (Without(!) Turbo core 2.0):
ubuntu 10.10 server x64
512G DDR3-1333
P6901
Average time/frame: 00:03:52

[09:15:07] Completed 0 out of 250000 steps (0%)
[09:18:59] Completed 2500 out of 250000 steps (1%)
[09:22:42] Completed 5000 out of 250000 steps (2%)
[09:26:16] Completed 7500 out of 250000 steps (3%)
[09:30:08] Completed 10000 out of 250000 steps (4%)
[09:34:06] Completed 12500 out of 250000 steps (5%)


For comparison:
Bulldozer "Interlagos" 16x4@ 1.8GHz* = 00:03:52
Opteron "Magny Cours" 12x4@ 2.2GHz = 00:06:40

Source

~58% higher single-threaded performance compared to K10, clock for clock.

[3dilettante]

Is that F@H benchmark single-threaded?

[rpg.314]

It's highly unlikely that it is serial, it's a pretty old client and I am sure that it is well threaded. It scores more with lower clocks. Although AVX may have tipped the balance if it was serial.

1.8G is pretty low for a speed racer. I was expecting almost the same clocks as MC at at launch. Although speeds might increase with more mature process.

[rpg.314]

That page also has Llano benchmarks. I would have liked to see a comparison of Llano with a discrete gpu, especially the power benches.

[entity279]

Originally Posted by rpg.314

1.8G is pretty low for a speed racer. I was expecting almost the same clocks as MC at at launch. Although speeds might increase with more mature process.

Hence there are 3 mouths+ till launch ...

[Miksu]

Nice to see that some software vendors are already taking advantage of the new features provided by Bulldozer (and Sandy Bridge). From the Visual Studio 2010 Service Pack 1 readme:

Visual Studio 2010 SP1 adds intrinsic functions or intrinsics to enable the extensions on the AMD and Intel new microprocessors that will be released next year. The intrinsic functions allow highly efficient computing without the overhead of a function call. For more information about the intrinsics function, visit the following website:
Compiler Intrinsics

For more information about the extensions, visit the following third-party websites:
Intel AVX
AMD Bulldozer instruction sets

[hoho]

Originally Posted by Miksu

Nice to see that some software vendors are already taking advantage of the new features provided by Bulldozer (and Sandy Bridge). From the Visual Studio 2010 Service Pack 1 readme:

I'm fairly certain GCC has included AVX support for at least couple of years now, not sure how good it is though.

[itsmydamnation]

interesting couple of posts from JFAMD on anandtech:

We have a 256b FP datapath (pipes 0 and 1) AND a 256b INT datapath (pipes 2 and 3), so

2 128b FP + 2 128b INT
or
1 256b FP + 2 128b INT
or
1 256b FP + 1 256b INT
or
2 128b FP + 1 256b INT

The INT here is an integer unit for doing the integer portion of math inside an SSE instruction, that is not the integer clusters that you would commonly call cores.

Plus there is a really cool feature around moves. Technically, we can do 4 128b SSE moves per cycle with a ZERO cycle latency. This is known as “MOVE ELIMINATION”.

And to further clarify directly:

Also there are some features AMD downplayed so far in my opinion. It is because obviously AMD has not only 2 FPU pipes and 2 MMX pipes. Those MMX pipes don't do MMX they are full 128 Bit integer SSE pipelines
(true).

So all register moves and load/stores can be executed also in those two pipelines
(not really, reg-reg moves for SSE and AVX-128 can be done with mov-elimination

Load – doesn’t actually require an execution pipe in the FP at all – but is limited to 2 128b loads/cycle max throughput.
Store – does take an execution pipe, but can only execute down 1 of the pipes. That & LS restrictions limit it to 1 128b store/c throughput)

I recently read a source that those two don't do 64 Bit MMX but 128 Bit SSE! Really don't know why AMD was so quiet about that so far and obfuscated that by using the wrong term "MMX". Therefore AMD can do 4 * 128 Bit SSE/cycle!

(yes, “MMX” is likely a bad name to use in describing the BullDozer micro-architecture and is somewhat misleading. Yes, we can do 4 128b arithmetic operations/cycle: 2 “floating-point” and 2 “SSE/AVX-128 integer”. Or/instead/in-combination we can also do 2 x87 “floating point” and 2 mmx “integer” per cycle – and by mmx I really mean the architected “mmx”).



And that is the sound of me clapping my hands like a blackjack dealer and saying "all done", can't get any further into this topic.