[liolio]

Hello everybody,

While surfing on real wolrd technologies today I found out that the cell roadmap has been update, look here after the page ten:
http://www-06.ibm.com/jp/solutions/d..._JHC_Japan.pdf

Looks like Cell2 could be 4PPU 32 SPU
The chip is planned for 2010/11
they aim for the TFlop.

They plan for faster SPE communication, more on chip memory, and better PPU (makes sense...)

[catisfit]

It's labelled as concept, but it makes sense.

SW compatibility between current and next-gen Cell
�� 100% backward compatible
�� Performance on PPE significantly better
�� Performance per SPE equal or better
– Significantly better on applications that benefit from new instructions
�� Better inter-SPE latency
�� More on-chip memory
�� Better main memory latency and bandwidth

Nice slide breaking down Folding@Home performance too.

[one]

Cool find!

Note: Traditional Codes run the PPU & NG PPU’ (C1 core)

IBM PowerXCell 32iv (4PPE’+32 eSPE)
~3.8 GHz
1 TFlop (est.)

[Entropy]

Page 11 has the interesting, or rather tantalizing info.
The PPE has been beefed up, communication between units has improved further, new SPE instructions, and perhaps most intriguing, better main memory latency and bandwidth. I really wonder what their new memory subsystem looks like, this could be just what the doctor ordered for a lot of scientific computation. The 2010-2011 timeframe however hints at PS4 deployment - if scientific computation had been the main target, the slide indicates that 45nm manufacturing is available a year and a half earlier. Perhaps the "concept" design depends on Sony committing to using it.

[Carl B]

Pages 16 and 17 speak to several of the practical strengths of the architecture.

For pages 11 and 12, I'm not sure it's clear whether the 32iv is part of the next-gen Cell or not, or whether it's just an extension of the 8i. Or whether those two ideas are even functionally different...

I read page 11 to be the arc of the current architecture though, with page 12 speaking to future, more fundamental changes. Changes I would expect for us to see beginning at 32nm and the development of the PS4. Good find by the way though liolio; nice to see IBM lay out the industries and business segments they're looking to expand Cell into.

[patsu]

The forward looking slides read like a wish list though. Nothing concrete/measurable yet except for the target number of cores, clock speed and estimated FLOPs.

I think many people are looking forward to:
* A more powerful PPU
* Larger Local Store
* Faster interconnect

I really like the slides, especially the "Solution Examples". They are real and yet exciting.

[Carl B]

I don't know if the "more on chip memory" refers to the local storage though; I'd think L2 cache in general to complement the more robust PPE. I spoke with one of the Cell team members last year and at least at the time they didn't feel the need for local store enlargement due to the negative effects it might have on latency. Not that views may not have changed on the matter since then...

For the moment I'm separating out the 32vi as a progression of the current Cell, and the 'forward looking' slide to some future chips not indicated on the roadmap.

[one]

As for PowerXCell 32iv it should be compared with the one on the older roadmap.
http://www.lanl.gov/orgs/hpc/roadrun...7%20(LAUR).pdf
(See page 10)

The older version was

Next Gen
(2PPE’+32SPE’)
45nm SOI
~1 TF-SP (est.)

in 2010. But PowerXCell 32iv is almost 2011. My guess is they are planning 32nm for it. Since Roadrunner proved its concept, the next logical step for IBM as a vendor is to cut the cost by removing Opteron nodes while increasing PPE for control jobs unless x86 compatibility is crucial.

It's now clear that PowerXCell 32iv has eSPE, DP-enhanced SPE. As games won't need DP, I think the 2PPE’+32SPE’ next-gen Cell with features in the page 11 at 45nm SOI is a good candidate for the PS4/PS3.5 CPU in the main trunk of the Cell/B.E roadmap.

[Lucid_Dreamer]

I think manufacturing an extra Cell chip with a different configuration would not allow them to push the cost down (through volume) like they are doing with the current Cell. Therefore, I believe they might go with the 4 PPE 32 SPE config. for both uses.

[Crossbar]

Originally Posted by liolio

They plan for faster SPE communication, more on chip memory, and better PPU (makes sense...)

Thanks for the link.

No mentioning of IBMs SOI EDRAM though.

32MB of 3:rd level cache would offload the memory IO quite a bit.

Edit: Found this new article on the EDRAM topic.

At the 45 nm generation, Patton said IBM is able to meet its logic technology goals by implementing strain technology. “Embedded DRAM was our No. 1 priority at 45, because high density memory on the same chip offers a very big performance advantage.

At several points over the last 18 months, IBM has said it would insert high-k at the 45 nm generation. IBM’s vice president of technology T.C. Chen put a great deal of pressure on himself and other IBM technologists to bring in high-k/metal gate technology at the 45 nm node. Apparently, they will get their satisfaction at the 32 nm generation, perhaps not quite as soon as they had hoped, but as Patton argues, soon enough. If the SOI eDRAM – which has a reported sub-3 nm access time – carries the water for IBM’s Power processors for awhile, that may be all right too. Innovation has many forms.

[handglobe]

The link doesn't work for me. By chance did anyone save a copy of the pdf?

[rpg.314]

I wish to go through the new roadmap in the first post, does any body have it by any chance? The link is not working for me.

[Carl B]

Hey Rpg.314 (and handglobe), sorry guys but the .pdf seems lost to the void of the Internet. You don't really need the picture though to tell you the truth - the discussion we had concerning it highlights all the key points one could have gleaned from it. I would have saved it myself if I thought it would disappear, but it is what it is.

[silhouette]

Btw, 4-PPE+32 SPE chip would be backwards compatible with 360 CPU too (given that it includes the enhancements done to current PPE).

[Carl B]

The XeCPU includes instruction support not present on the Cell PPE, inclusive to everyone's knowledge of the 32-SPE Cell discussed here.

[catisfit]

Here it is (I have the PDF):

P10:


P11:


P16:


P17:


P22:


I don't think any other pages were mentioned in the discussion above.

[Carl B]

Thanks Catisfit, I'm sure a lot of folk that missed these the first time around will appreciate your effort here.

[rpg.314]

Originally Posted by Carl B

Thanks Catisfit, I'm sure a lot of folk that missed these the first time around will appreciate your effort here.

Yes, and I am one of them.