[nAo]

Intel will present a paper about Larrabee at Siggraph this summer:

Larrabee: A Many-Core x86 Architecture for Visual Computing

This paper introduces the Larrabee many-core visual computing architecture (a new software rendering pipeline implementation), a many-core programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as fixed-function co-processors. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads and greatly increases the flexibility and programmability of the architecture as compared to standard GPUs.

I'm sure this post will put a smile on Geo's face

[3dilettante]

Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as fixed-function co-processors.

I hope there are some nifty disclosures on just how much is under that umbrella.

[ShaidarHaran]

Nice find, nAo.

Originally Posted by 3dilettante

I hope there are some nifty disclosures on just how much is under that umbrella.

Definitely looking forward to opening that can of worms.

DK over @ RWT has a discussion thread on the subject (credit nAo again).

speaking of can of worms.... interesting supposition by Doug Siebert (long-time RWT poster):

Sure, there may still be some discrete Larrabee parts if there is demand for them in the HPC world or Intel really does plan on pursuing the discrete GPU market. I'm skeptical of that, but I guess once Nvidia is dead in a few years Intel won't want to let AMD have that market to itself, even though it will be much smaller than it is today!

[nAo]

From the abstract it seems this talk/paper is more software oriented than hardware oriented. I wouldn't be surprised if we won't learn any new technical detail about Larrabee's hardware architecture.
On the other hand I can't wait to know also more about its software architecture to get a glimpse of how Intel will likely expose the hardware to software engineers. (I'm not exactly a CUDA fanboy)

Regarding fixed function units we are going to see some TMUs and probably not much more than that. Adieu rasterizer..

[ShaidarHaran]

Originally Posted by nAo

From the abstract it seems this talk/paper is more software oriented than hardware oriented. I wouldn't be surprised if we won't learn any new technical detail about Larrabee's hardware architecture.
On the other hand I can't wait to know also more about its software architecture to get a glimpse of how Intel will likely expose the hardware to software engineers. (I'm not exactly a CUDA fanboy)

Regarding fixed function units we are going to see some TMUs and probably not much more than that. Adieu rasterizer..

Even if they don't give us anymore details on Larrabee's micro-architecture, I'm sure they'll at least provide relevant instruction throughput numbers. Rather useful in your line of work, I'd think

[3dilettante]

Originally Posted by nAo

From the abstract it seems this talk/paper is more software oriented than hardware oriented. I wouldn't be surprised if we won't learn any new technical detail about Larrabee's hardware architecture.
On the other hand I can't wait to know also more about its software architecture to get a glimpse of how Intel will likely expose the hardware to software engineers. (I'm not exactly a CUDA fanboy)

Regarding fixed function units we are going to see some TMUs and probably not much more than that. Adieu rasterizer..

Even knowing the outlines of how TMU functionality is accessed by the x86 threads will be informative, unless the paper turns out to be entirely made of fluff.

[Mat3]

There'll be some scalar processors in there too of course, but it's interesting that they will be depending on a wide vector unit to do a lot of the work.

[ShaidarHaran]

Originally Posted by Mat3

There'll be some scalar processors in there too of course, but it's interesting that they will be depending on a wide vector unit to do a lot of the work.

Isn't it more likely that the "ALUs" will simply support both vector and scalar instructions?

[3dilettante]

Originally Posted by Mat3

There'll be some scalar processors in there too of course, but it's interesting that they will be depending on a wide vector unit to do a lot of the work.

The scalar units exist alongside a wide SIMD unit in each core.
Larrabee's descriptions don't hint at any scalar-only cores.

[nAo]

It seems Intel licensed Pixomatic IP, another indirect confirmation that Forsyth and Abrash are working on Larrabee's software rasterizer:

http://softwarecommunity.intel.com/i...ghai_short.ppt

[darkblu]

Originally Posted by nAo

It seems Intel licensed Pixomatic IP, another indirect confirmation that Forsyth and Abrash are working on Larrabee's software rasterizer:

http://softwarecommunity.intel.com/i...ghai_short.ppt

i'd have been very surprised if Abrash was not working on a software larrabee rasterizer : )

[^M^]

Intel bought Pixomatic to RAD in the end of 2005 : http://www.radgametools.com/pixomain.htm

But RAD seems to have kept the right to license current (at the time) versions.

[nAo]

Ouch, they also have a DX9 implementation, I wasn't aware of that
I wonder if Abrash&Co. had the opportunity to ask for specific hardware optimizations that would speed up software rasterization.

[ShaidarHaran]

Originally Posted by nAo

Ouch, they also have a DX9 implementation, I wasn't aware of that
I wonder if Abrash&Co. had the opportunity to ask for specific hardware optimizations that would speed up software rasterization.

Would the new Radix 16 Divider and Super Shuffle Engine in Penryn family CPUs qualify?

[3dilettante]

Division is helped by the Radix 16 divider and variable-latency divides, though how does that look specific to graphics?

Super-shuffle isn't much of a graphics-only optimization as it's bringing Intel's shuffle latencies within the same range or better than what AMD's had for years.
Conroe had pretty long latencies. Netburst's latencies were pretty brutal.

There was that instruction for blending, which might seem closer to a graphics optimization.

[Humus]

Well, nothing can be said to be graphics specific since it's useful for other purposes as well, but there are a few candidates for where graphics might have been one of the main motivators. Super-shuffle would count into that, the blending instructions, and most certainly the DPPS instruction, which can implement DOT2/DOT3/DOT4 stuff. The fast divider is a bit too generic to say it's graphics related, although it'll help for a number of important tasks.

The dot product instruction is particularly interesting to note, especially given that Intel never really seemed to show much interest for graphics in previous SSE instruction sets.

[Geo]

Damnit, I'm going to have to buy a Larrabee viddy card. . . .just because. A) To show what an iconoclast I am. B). As a collectors item of when Intel began their conquest of gpus C). As a collectors item of Intel's Folly in thinking they could conquer gpus. D). Because I enjoy bitching about IHV's not providing robust software support and compatibility, and this is almost certain to be "a target rich environment" with Larrabee.

Or some combination of the above.



Has anybody heard a productization name rumour yet? "Bitchin' Fast 3D" or somesuch?

Oh yes, and y'all feel free to leak that paper to me/B3D in advance. I understand Dougie sees B3D ninjas behind every potted plant.

[Andrew Lauritzen]

Ahahaha... ahh man Geo, you're too harsh

[nAo]

Too bad we have to wait another month to read that paper..

[Geo]

Originally Posted by Andrew Lauritzen

Ahahaha... ahh man Geo, you're too harsh

Man, anytime Intel wants to step up to our interivew, it's been out there for them to do so.

The god's honest truth is I want them to succeed because I love high-end graphics and the more serious deep-pocket players there are the happier I am.

And I've been saying for over a year now that the vibes are Intel is genuinely alarmed this time and that means they won't take one swing and give up. My only point is they need to be psychologically prepared to get their nose bloodied in round one, because they probably will, and it will likely be on the software side no matter how sweet their hardware is on the theoreticals.

[Rufus]

Originally Posted by ShaidarHaran

Would the new Radix 16 Divider and Super Shuffle Engine in Penryn family CPUs qualify?

Not likely if Jon Stokes's confirmation of the rumor mill is correct that Larrabee is an original Pentium core with a vector unit tacked on:
http://arstechnica.com/news.ars/post...ech-sorta.html

[nAo]

From Ars

Intel will claim that Larrabee has 20x the performance per watt of a Core 2 Duo and half the single-threaded performance.

20x perf at what? texture sampling?

It also has a 4MB coherent L2, and three-operand vector instructions.

Only 128kb of L2 per core? I'd double that..

[ShaidarHaran]

Originally Posted by Rufus

Not likely if Jon Stokes's confirmation of the rumor mill is correct that Larrabee is an original Pentium core with a vector unit tacked on:
http://arstechnica.com/news.ars/post...ech-sorta.html

That's a gross over-simplification at best, completely wrong at worst.

[ShaidarHaran]

Originally Posted by nAo

From Ars

20x perf at what? texture sampling?

No doubt it's peak SP GFLOP rate.

Originally Posted by nAo

Only 128kb of L2 per core? I'd double that..

More cache is always better (until you have to increase latency to accomodate size), but 128KB per SIMD seems adequate to me...

[zsouthboy]

Originally Posted by ShaidarHaran

That's a gross over-simplification at best, completely wrong at worst.

What's wrong with it exactly? It's based on the old Pentium + years of bugfixes, right?