[vers]

4 visualizer= 4pixel,4 texel / CYCLE ???

[london-boy]

sentences usually have a subject, a verb and an object.... then u can play around with it to create things called "statements"... u know, so people can actually understand what u're saying....

anyway, to stay on topic, we dont know fuck all about the PS3 visualiser, so why bother....


aint u the one who posted that thing about bump mapping on PS2? or was it someone else?

[Panajev2001a]

Yes... the Visualizer has 4 pipelines...

A 4x1 configuration is possible...

You clock that puppy at 1 GHz and that means 4 GPixels/s and 4 GTexels/s

Not bad considering the FP and Integer power the 16 APUs present should bring to the table


He is referring to the Visualizer chip shown in the Cell patent

[jvd]

Originally Posted by london-boy

sentences usually have a subject, a verb and an object.... then u can play around with it to create things called "statements"... u know, so people can actually understand what u're saying....

anyway, to stay on topic, we dont know fuck all about the PS3 visualiser, so why bother....


aint u the one who posted that thing about bump mapping on PS2? or was it someone else?

Leave people with poor english skills alone. Not everyone speaks english well on this board. We have people from all over.

[jvd]

Originally Posted by Panajev2001a

Yes... the Visualizer has 4 pipelines...

A 4x1 configuration is possible...

You clock that puppy at 1 GHz and that means 4 GPixels/s and 4 GTexels/s

Not bad considering the FP and Integer power the 16 APUs present should bring to the table


He is referring to the Visualizer chip shown in the Cell patent

You've got to get it clocked at 1ghz first. Thats not an easy thing to do even at .65nm (if thats what they are using for the graphics chip)

[Panajev2001a]

The GS could clock at 150 MHz using 2,560 bits e-DRAM and using 250 nm technology and no SOI, we are talking about 1,024 bits this time and using 65 nm technology with SOI...

Also the e-DRAM can be clocked a bit lower than the rest of the chip... if they really need it...

[megadrive0088]

It just seems odd to me that Visualizer (or GS3) would have only 4 pipelines. perhaps the patent was simply an illistration/example of how CELL could be transformed into a graphics processor.

Does that actually mean PS3's GPU will only have 4 pixel engines? even with the 1 GHz clock, it doesnt seem like much fillrate. I would tend think that Sony has not revealed the architechure of PS3's graphics processor yet.

I was thinking at least 16 pipes (as much as GS in PS2 has) at 1 to 1.5Ghz
with 1 texture unit each at least. if not, perhaps a new texture unit that can produce more than 1 texture/effect per cycle (like Flipper's TEV)

16 pixel engines * 1 or 1.5 Ghz gives us 16-24 gigapixels and at least
16-24 gigatexels if 1 texture unit per pipe and 1 texture per cycle.

but I know Panajev will disagree saying that 4 gigapixels/4 gigatexels is enough with the integer/FP units of the APUs and PUs of Visualizer.

[Panajev2001a]

dp

[Panajev2001a]

4 GPixels/s == 1.6x pixel fill-rate of the GS

4 GTexels/s == 3.2x texel fill-rate of the GS

1 GHz * 16 * 8 = 128 GFLOPS


1 GHz * 16 * 8 = 128 GOPS


4 GTexels/s = 1920x1080p * 60 fps * 32 ( over-draw )

This puppy can support an overdraw of 32x at 1080p...

Or an over-draw of 10x with 3.2 texture layers per pixel in average...

With micro-polygons each micro-polygon is likely to be single textured so the 32x maximum overdraw makes a bit more sense...

[vers]

Originally Posted by Panajev2001a

4 GPixels/s == 1.6x pixel fill-rate of the GS

4 GTexels/s == 3.2x texel fill-rate of the GS

1 GHz * 16 * 8 = 128 GFLOPS


1 GHz * 16 * 8 = 128 GOPS


4 GTexels/s = 1920x1080p * 60 fps * 32 ( over-draw )

This puppy can support an overdraw of 32x at 1080p...

Or an over-draw of 10x with 3.2 texture layers per pixel in average...

With micro-polygons each micro-polygon is likely to be single textured so the 32x amximum overdraw makes a bit more sense...

for raytracing engine need 1920*1080*60= 120 megapixel/sec

[Panajev2001a]

120 MPixels/s * 32 overdraw = ~3.8 GPixels/s so ?

[Vince]

Panajev2001a, I think your getting ahead of yourself. We don't know what the Visualizer's "Pixel Engines" are composed of.

[V3]

A 4x1 configuration is possible...

You clock that puppy at 1 GHz and that means 4 GPixels/s and 4 GTexels/s

With that arrangement and speed, you don't need embedded frame buffer anymore.

Since they are implying embedded image cache, I think its abit more than 1x1 config for each pixel engine.

[Vince]

Originally Posted by V3

Since they are implying embedded image cache, I think its abit more than 1x1 config for each pixel engine.

Exactly, very good observation. I personally feel we'll see the rebirth of multiple GS-like pipelines in each "PixelEngine."

[Panajev2001a]

The Image cache is not the embedded frame-buffer... we have e-DRAM for that...

That e-DRAM will be needed... high resolution textures, FSAA, 3D Textures, vertex buffers ( tons of micro-polygons flowing from the Broadband Engine ) etc...


Pixel Engines: support for texture filtering ( up to tri-linear + anisotropic [256+ bits of texel data, might come in compressed format] ), up to 96-128 bits for color ( 24-32 bits per component ) and 32 bits Integer or FP Z-buffer, CLUT, S3TC or VQ ( might be done in software by the APUs... )...

What do you guys think ?

[Panajev2001a]

Unless you are allowing each pipeline inside the Pixel Engine to work on a different triangle ( the way I see it is 4 APU for each Pixel Pipeline ) you are going to face troubles using micro-polygons...

4-8 pixel pipelines in each Pixel Engine rendering a sub-pixel or pixel size triangle ?

[V3]

The Image cache is not the embedded frame-buffer... we have e-DRAM for that...

Its not, if it is, they would not have put image cache and circuitry in there tightly coupled with the pixel engine.

That e-DRAM will be needed... high resolution textures, FSAA, 3D Textures, vertex buffers ( tons of micro-polygons flowing from the Broadband Engine ) etc...

Yes. you probably able to write back the frame buffer from the image cache to e-DRAM, but the Pixel engine should write to image cache.

If it is only 1x1 config, Pixel engine can write to the e-DRAM directly, or write to the external RAM. The Rambus stuff you mentioned gives more than enough bandwidth for 4x1 config. Once you use things for shadows. 4GPixel/s isn't alot even for 640x480.

That Pixel engine, is most likely some enhanced PS2 GS.

[Panajev2001a]

If it is only 1x1 config, Pixel engine can write to the e-DRAM directly

Bingo

The External Rambus Yellowstone RAM will be busy enough loading data from the Blu-Ray disc and streaming it to the Broadband Engine and the Visualizer to be able to have the Pixel Engines render directly to it...

It is only 25.6 GB/s

Why would we need more than 1 pixel pipeline per Pixel Engine when most polygons could be 1 pixel or half a pixel in size ?

The Image Cache is needed to cache textures ( and from which take them and filter them... maybe they are stored uncompressed here... ) and the tile of pixels and an on-chip Z-buffer of similar size to the tile of pixels that the Pixel Engine is working on ( say 32x32 or 64x64 for the tile size in pixels ? )...

[Panajev2001a]

The Image cache is too small to cache textures and a full size frame-buffer and Z-buffer...

I think it will have an on chip tile buffer and Z-buffer ( both 32x32 or 64x64 )... no deferred rendering in HW, just tiling...

[Fafalada]

Does that actually mean PS3's GPU will only have 4 pixel engines? even with the 1 GHz clock, it doesnt seem like much fillrate. I would tend think that Sony has not revealed the architechure of PS3's graphics processor yet.

In the patent, those 4 pixel engines execute 32flops of shader ops per cycle, which would be 5x more then say a NV2x class rasterizer, making that fill equivalent to over 20GPix.
And I haven't even counted integer ops :P

Still sounds like not much?

[chaphack]

Hey faf! Where are my E3 impressions????

[Panajev2001a]

Ahem... Fafalada... I think we will not see a 4 GHz Visualizer... a 1-2 GHz chip is more probable IMHO...

Still that is 8-16 GFLOPS and 8-16 GOPS per APU and thus 32-64 GFLOPS and 32-64 GOPS per pixel pipeline...

I do not see as impossible things a ~4 GHz ( e-DRAM would be clocked at 1-2 GHz in this chip ) Broadband Engine and a 1 GHz Visualizer...

[Fafalada]

Pana, I was talking about FLOP/cycle (outside clock speed) (that 'S' at the end of FLOP was a typo that crawled in :P ). And I still assumed 1ghz at fill calc.
Either way, the point is that when you have so many ops per clock on a pixel the raw fill becomes much less of an issue.

Chap, all in good time, I am still getting my bearings with time zones and work and what not.

[chaphack]

I love you faf!

[Panajev2001a]

You liar... I saw you getting your groove going that nVIDIA party babe... all break-dancing Fafalada style

That is why you are SO tired

Seriously, I agree with you on the fill-rate issue... what I think about is nthat if we used 1 pixel or half a pixel micro-polygons this power would be all for shading ( even with regular OpenGL pipeline... the Broadband Engine would do T&L )...