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#76 | |
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Regular
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Quote:
Also, at the last CC NVidia said that all GPUs in manufacturing are 55nm now. And it's almost a year since GT200 should have launched, so a 55nm version arriving shortly shouldn't be surprising. Jawed |
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#77 |
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Senior Member
Join Date: Mar 2002
Location: msk.ru/spb.ru
Posts: 1,255
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So the result is that this is GT200b? =)
Here's another picture, with broken G80 side by side:
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#78 |
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Member
Join Date: Oct 2004
Posts: 241
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Well, it`s still pretty huge die.
When will we see a GT206 die? |
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#79 |
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Regular
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So, GT200b is still 512-bit?
Jawed |
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#80 |
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Member
Join Date: Oct 2004
Posts: 241
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#81 |
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Regular
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#82 |
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Member
Join Date: Apr 2007
Posts: 991
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#83 |
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Member
Join Date: Oct 2004
Posts: 241
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Hmm i think the better way for NVIDIA would be 384-bit memory bus in it`s GPUS. Cheaper to produce (die size and PCB) even using GDDR5.
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#84 |
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Regular
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#85 |
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Senior Member
Join Date: Mar 2002
Location: msk.ru/spb.ru
Posts: 1,255
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22x22 vs 22x21.5 for G80. It's big sure but it's not huge.
I dunno =) That's obvious, no? GT200b is supposedly exactly the same as G92b, G94b, G96b -- just a straight die-shrink without any changes to the architecture. GT206 should be the first GPU from NV with GDDR5 support. |
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#86 | |
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Member
Join Date: Oct 2004
Posts: 241
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Quote:
PS. I wonder about NVIDIAs Roadmap leaked from ELSA. There is GT212 scheduled for 1H09 but it seems that it will be still only shrinked GT200 wit the same DX10 architecture. It`s even strange because ATI has claimed that they are going to release Rv870 with DX11 support around the same time. |
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#87 | |
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Senior Member
Join Date: Mar 2002
Location: msk.ru/spb.ru
Posts: 1,255
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Quote:
AFAIR ATI never stated that RV870 will have DX11 support, only that they'll release DX11 GPUs in 2009. |
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#88 |
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Member
Join Date: Oct 2004
Posts: 241
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So GT206 is going to have "only" 256-bit memory bus? This means that there will be only 16 ROPs and it could be not enough with AA enabled. But i could be wrong of course.
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#89 |
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hardware monkey
Join Date: Mar 2007
Posts: 3,814
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Probably.
Not necessarily... The ROP partitions could be re-organized to accomodate 8 ROPs per 64-bit memory channel, and that would preserve the current 32 ROP design of GT200. Also there's the possibility of "fat" ROPs capable of processing more pixels/zixels per cycle, negating the reduction in actual ROP count to 16. |
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#90 |
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Senior Member
Join Date: Mar 2002
Location: msk.ru/spb.ru
Posts: 1,255
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GT206 will probably has only 4 64-bit ROPs. The number of ROPs however has nothing to do with their capabilities. Since GDDR5 provides nearly 2x increase in bandwidth per line these ROPs should have 2x more power and one GDDR5 ROP should be able to write 8 C / 32 Z per clock. Plus it may be smart (or not) to go with one clock 8 Z compare for MSAA and faster FP16 writing/blending. Using old ROPs with GDDR5 is pretty pointless.
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#91 | |
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hardware monkey
Join Date: Mar 2007
Posts: 3,814
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Quote:
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#92 |
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Senior Member
Join Date: Mar 2002
Location: msk.ru/spb.ru
Posts: 1,255
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You need to change the ROPs for double output of course. Otherwise you'll just waste GDDR5 bandwidth.
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#93 |
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hardware monkey
Join Date: Mar 2007
Posts: 3,814
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