[Nebuchadnezzar]

I don't really understand how this DDRII is working, can somebody explain me that?

[Neeyik]

From what I've understood (which might not be too much), DDR II uses two dedicated ports - one for reads and one for writes - which is supposed to allow concurrent read/writes to take place, rather than having just one port which has to read or write.

The theoretical maximum bandwidth of DDR II I should imagine would be calculated in the same manner as with previous memory types, ie. data transfer speed x number of bits per transfer.

[Nebuchadnezzar]

But I heared about DDRII 400 with 4,8 Gb/s thats 50% more than DDRI 400 (3.2 Gb/s)

[Nebuchadnezzar]

The Inq. :

http://www.theinquirer.net/27030211.htm

DDRII 400 4.8 Gb/s

[Basic]

Short answer: probably the same way as for DDR.

Longer answer:
I assume that Nebu is talking about DDRII DRAM.

While I haven't seen specs for DDRII DRAM I would be very suprised if it were dual ported. While that would give you higher bandwidth to each bit in memory, it won't rise the bandwidth per pin. So it wouldn't help were the problem is. Another hint that DDRII DRAM isn't dual ported is that DDRII SRAM isn't.
OK, there is one oddball version of DDRII SRAM that is dual ported, but it seems (I haven't found much info) as that version can't use the buses simultaneously. If it were able to do that, it would be QDRII SRAM.

So what is DDRII DRAM?
I'm not sure, but if the difference from DDR DRAM is the same as the difference between DDR/QDR SRAM and DDRII/QDRII SRAM, then it won't change the data rate per clock, and won't change the bus architecture. The difference would mostly be in timings.

[Basic]

I had only seen one reply when I wrote that, I'm off to register at Jedec to see their specs. We'll see what I'll find, but I can say one thing directly: Never trust theInquirer.

[Basic]

Maybe I'm stupid, but the only thing I found on DDRII at www.jedec.com was DDR_II_evolution.pdf, which isn't a real specsheet. But it's at least enough to say that the bandwidths reported at theInquirer is pure bullshit.

Big suprise!

Maybe there's some timings that make it faster regarding average acheived bandwidth, but definitely not wrt raw bandwidth.

That document also gives what I would concider the big difference between DDR and DDRII. I'll give an example.

Type / data rate / external clock / mem array clock
DDR DRAM / 400MHz / 200MHz / 200MHz
DDRII DRAM / 400MHz / 200MHz / 100MHz

This means that they can use a simpler memory array for the same external bandwidth. Or to put it in a more positive way, they can get higher external bandwidth with the same memory array.

The big drawback though is that the minimum burst length has increased from 2 to 4. This might not be so bad for PCs that (i think) usually reads/writes whole cache lines anyways. But for graphics cards (which needs more granularity), it's not so good.
Ask Simon F what he likes the idea, I think he's said a few times that the increased minimum burst length from SDR to DDR (1 to 2) makes DDR clearly slower than what the frequency might suggest.

[Neeyik]

Well I was never certain about what I picked up about DDR II...doing my own nosing around has picked up various bits and bobs:

DDR II SIO (dual ported) SRAM
http://www.qdrsram.com/datasheets/Cy...sio_latest.pdf

Enhanced DDR II
http://www.pc133memory.com/DDR-II/Q&A1.html

Press release
http://www.siliconstrategies.com/mar...G20020325S0065

[Basic]

OK, I was wrong refarding DDR II SIO SRAM. The pinout clearly has separate I/O, and the timing shows that they could be used simultaneously. But it's kinda strange that the only application example they show in that document has the I/O denoted as a common DQ-bus. And I'm not sure how this differs from QDR II SRAM.

Either way, that's the SRAM version and not interesting wrt 3D graphics.

But the Enhanced DDR II is quite interesting. The document I mentioned said that such tricks and virtual channel are explored. And that's something that's *realy* interesting. It would certainly help out when doing massive multitexturing. Too bad that's one of the areas where patents has hold back technology advancements. Some of those (obvious) tricks are patented, and I remember that some companies wanted to do their own cached DRAM, but got sued by patent holders. And the result is that we still get massive hits when we want to work in a few pages simultaneously.

[elimc]

I looked at some JEDEC specs for DDRII and the interesting thing is that it appears to be multiplexed. I mean, I think the current DDR SDRAM is multiplexed but DDRII appears to be multiplexed by four. This would theoretically increase bandwidth by four. Is this practical? I don't think so. I imagine that they will reduce pin count while increasing bandwidth per pin making it more like RDRAM. Also, I've heard they may add a strobe.

[Basic]

elmic:
Have you found any docs other than that one called DDR_II_evolution.pdf?

Choosing the pin count on different devices is of course up to the designer. But don't expect DIMMs or graphic cards to reduce the pin count (other than low end graphics cards).

I don't expect any huge bump in bandwidth per pin when DDRII arrives, it's more like a trick to guarantee a continued steady increase.

[elimc]

elmic:
Have you found any docs other than that one called DDR_II_evolution.pdf?

Yea. There was a guy I talked to at sharky's forum. He had a whitepaper from the JEDEC website describing DDRII and was curious about the increase in speed per pin and what it meant. We discerned that it was multiplexed by four. Unfortunately, the thread is no longer there and I made the mistake of not bookmarking the paper. There was also the option to multiplex the bus by two and by one effectively creating different speed grades.

Choosing the pin count on different devices is of course up to the designer. But don't expect DIMMs or graphic cards to reduce the pin count (other than low end graphics cards).

If the bandwidth per pin is indeed increased by a good amount, I would expect them to need to reduce pin count. They are already have some real problems verifying high end DDR SDRAM.

I don't expect any huge bump in bandwidth per pin when DDRII arrives, it's more like a trick to guarantee a continued steady increase.

Well, I guess we'll see, eh? BTW, have you joined JEDEC.org? If you join (for free) you can gain access to presentations and white papers. I haven't joined.

[Basic]

I think I found the discussion, was it with GiGNiC? He did point to the same pdf as I talked about (which by the way is written by a guy from ATI). I just hoped to find some real specs.

Btw, search for "DDRII whitepaper" at sharky's, and you'll find the thread.

The databus is multiplexed by four just as you say, but in a way that makes it look like an old DDRI bus. The only difference being the minimum burst length of four (as opposed to a DDRI bus' two). You could look at the example of DDR400 vs DDRII400 I gave above.

You talk about "theoretically increasing bandwidth by four" as if you expected bandwidth to get a hefty bump as DDRII hits the street, but it's not that dramatic. For DIMMS, it will be a matter of DDR400 being phased out by DDRII400 to some extent, and DDRII533 to a greater extent. That means that the first step will have exactly the same bandwidth per pin, and next step is (in percent) the same as from PC100 to PC133. And at the same time, the memory is changed to a simpler one (memory array running at half the speed, bursts can no longer be interrupted).

So there's no doubt that DDRII-DIMMS will stay at 64bit, and high end graphics will not step down to less than 128 bit.

Btw, that pdf also said that x32 package are in development (and it's a rather old paper, so it might be ready now).

[elimc]

Btw, search for "DDRII whitepaper" at sharky's, and you'll find the thread.

Oh, thank you.

You talk about "theoretically increasing bandwidth by four" as if you expected bandwidth to get a hefty bump as DDRII hits the street, but it's not that dramatic. For DIMMS, it will be a matter of DDR400 being phased out by DDRII400 to some extent, and DDRII533 to a greater extent. That means that the first step will have exactly the same bandwidth per pin, and next step is (in percent) the same as from PC100 to PC133. And at the same time, the memory is changed to a simpler one (memory array running at half the speed, bursts can no longer be interrupted).

Right. I think that they will reduce the amount of pins in order to deal with problems posed with higher data rates. So DDRII will not reach it's maximum theoretical limit of four times faster than DDRI.

[mboeller]

Originally Posted by Basic

I think I found the discussion, was it with GiGNiC? He did point to the same pdf as I talked about (which by the way is written by a guy from ATI). I just hoped to find some real specs.

Btw, search for "DDRII whitepaper" at sharky's, and you'll find the thread.

The databus is multiplexed by four just as you say, but in a way that makes it look like an old DDRI bus. The only difference being the minimum burst length of four (as opposed to a DDRI bus' two). You could look at the example of DDR400 vs DDRII400 I gave above.

You talk about "theoretically increasing bandwidth by four" as if you expected bandwidth to get a hefty bump as DDRII hits the street, but it's not that dramatic. For DIMMS, it will be a matter of DDR400 being phased out by DDRII400 to some extent, and DDRII533 to a greater extent. That means that the first step will have exactly the same bandwidth per pin, and next step is (in percent) the same as from PC100 to PC133. And at the same time, the memory is changed to a simpler one (memory array running at half the speed, bursts can no longer be interrupted).

So there's no doubt that DDRII-DIMMS will stay at 64bit, and high end graphics will not step down to less than 128 bit.

Btw, that pdf also said that x32 package are in development (and it's a rather old paper, so it might be ready now).

Sorry if I misunderstood You, cause I only overlooked Your post and the thread, but you seem to imply that DDR-II is the same as DDR and no form of QDR-memory which could send 4words per pin per cycle (like the new form of RDRAM in development now).

[Basic]

elimc:
But there's nothing in that "whitepaper" that says anything about a "maximum theoretical limit of four times faster than DDRI". You could say that there's a theoretical limit of TWO times faster than DDRI, if the only speed limiting part were the memory array. But as they say in the paper, it's supposed to be a evolutionary progress, not revolutionary. The first DDRII memories will run at similar dataspeeds per pin as the DDRI memories present at the same time.

mboller:
Yes, you read it right. It's only 2 bits per pin and clock cycle, just as DDRI. It's 4 bits per pin and memory array cycle, but that's because the memory array runs at half speed.
One more thing, QDR is a trademark for a kind of memory bus that you probably didn't mean (and that doesn't transfer 4 bits per clock and pin), so it's best to stay clear from that term.

[elimc]

But there's nothing in that "whitepaper" that says anything about a "maximum theoretical limit of four times faster than DDRI".

True, LOL. I just made that up.

The first DDRII memories will run at similar dataspeeds per pin as the DDRI memories present at the same time.

So you think the first DDRII modules will run as fast as current highend DDR400? And what about the multiplexing? It would seem to indicate more bandwidth per pin. Or am I reading it wrong?

[Basic]

And what about the multiplexing?

As I think I've said a couple of times. When comparing for instance DDR400 vs DDRII400 (2 vs 4 way multiplex), the higher multiplexing is used to run the memory array at half the frequency, still at same data rate per pin.

Just to be a little more clear. When talking about the memory array in a DRAM, you mean the part of the chip that actually stores the data, as opposed to the external interface out from the chip. The design of the memory array is not much related to the interface, and the same array could be used for SDR100, DDR200, DDRII400 and RDRAM800.
(RDRAM800 break up the array in more banks though.)

[NTD]

So regular SDR DRAM x 2 = DDR DRAM x 2 = DDRII DRAM or QDR DRAM? I'm talking bandwidth here.

[Basic]

I'm not sure what you meant there, but I can say that such comparison isn't interesting if you don't say what speed the different memories are:

• Same memory array clock speed.
• Same external bus clock speed.
• Same datarate. (Which is the usual way to denote the speed now.)
• Same cost at certain point in time.
• Fastest available at certain point in time.

And again, QDR DRAM doesn't exist, and probably never will. "QDR" is trademarked for a SRAM data bus. If someone have some information that says otherwise, then please tell.

[elimc]

As I think I've said a couple of times. When comparing for instance DDR400 vs DDRII400 (2 vs 4 way multiplex), the higher multiplexing is used to run the memory array at half the frequency, still at same data rate per pin.

Just to be a little more clear. When talking about the memory array in a DRAM, you mean the part of the chip that actually stores the data, as opposed to the external interface out from the chip. The design of the memory array is not much related to the interface, and the same array could be used for SDR100, DDR200, DDRII400 and RDRAM800.
(RDRAM800 break up the array in more banks though.)

Yea, I think there was a miscommunication between me and you. I think you're stating what I was trying to get at.

[NTD]

Originally Posted by Basic

I'm not sure what you meant there, but I can say that such comparison isn't interesting if you don't say what speed the different memories are:

• Same memory array clock speed.
• Same external bus clock speed.
• Same datarate. (Which is the usual way to denote the speed now.)
• Same cost at certain point in time.
• Fastest available at certain point in time.

Well, like I said, bandwidth and of course at identical clockspeeds. DDR running at 133MHz gives you, theoretically, twice the datarate SDR does at the same clockspeed.

[Entropy]

DDR-400 and DDRII-400 DRAM output data at the same rate.

(I thought it deserved to be said on its' own.)
The changes in the DDRII spec help ensure signal integrity and greater ease of scaling the clock upwards.

You guys got mighty technical for a while there, to the point where even the somewhat initiated could get confused.

Entropy

[pascal]

IIRC DDR II is:
- 400Mbits/pin for mult-drop configurations, or 3.2GB/s for 64bits bus
- 800Mbits/pin for point-to-point configurations, or 6.4GB/s for 64bits bus

The DRAM core runs at 1/4 the data bus frequency because it uses a prefetch of 4 (burst 4 only, righest common denominator and lower test cost). Also no 1/2 latency and no interruption commands (lower test costs too).

Maybe this PC6400 will use a prefetch of 8???

[pascal]

Some kentron pdf file show an alternative using phase shifting for memory
http://www.via.com.tw/en/presentatio...ronQuadDDR.PDF

edited: it looks like they are still discussing about the 8 banks. Also the 4, 8 and 16 burst are available?? See page eleven of this presentation:
http://www.via.com.tw/en/ddr/DDR333%20Summit%202002/11