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Old 30-Apr-2007, 17:01   #3851
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From German site






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Old 30-Apr-2007, 17:10   #3852
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The last doesn't seem official as the rest, wasn't the general impression that it has 16x32bit, not 8x64bit controllers?
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Old 30-Apr-2007, 17:13   #3853
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Integer support only via the fat ALU?
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Old 30-Apr-2007, 17:14   #3854
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Originally Posted by R300King! View Post
From German site...
Thanks! VLIW was the magic word I was looking for.
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Old 30-Apr-2007, 17:14   #3855
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Originally Posted by Kaotik View Post
The last doesn't seem official as the rest, wasn't the general impression that it has 16x32bit, not 8x64bit controllers?
Honestly, not sure, I just reposted the images from www.3dcenter.de forum. The last image posted was by a different forum member than the first images.
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Old 30-Apr-2007, 17:32   #3856
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Originally Posted by nAo View Post
Integer support only via the fat ALU?
The fat alu is probably the special function unit

2k internal ringbus,
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Old 30-Apr-2007, 17:33   #3857
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Originally Posted by silent_guy View Post
That covers the instruction type. What about the register selection?
It's not just registers for operands, though. It's also possible to have indexed constants. There are 16 constant arrays (actually that's just what can be bound to a shader), each constant can have 4096 entries and each entry can have 4 elements. I didn't realise you meant to include stuff beyond the type!

Also, it seems that R6xx will be able to directly read/write virtual memory addresses, which will be a chunk of bits. Maybe I've got the wrong end of the stick though and only TUs and RBEs can address memory.

Quote:
If each is doing a MAD and they are truly independent, you're looking at 3 operands and 1 destination * 5 = 20 register selections. If the register file is 32 deep, you're looking at 100 bits just for for that.
But that's only be the case for a MAD.
Yeah, hurts my head. Hoping we'll get some nice detail on this.

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It wouldn't surprise me if a MAD instruction will still have some restrictions wrt register dependence.
In the past ATI has been very proud of the fact that its ALU pipeline has not had any operand fetch bandwidth restrictions. I kinda hope they've maintained that tradition.

Theoretically, R3xx...R5xx are all capable of fetching 5 vec4 operands per clock, to feed the MAD+ADD pipeline. But I've never seen it stated in such cold, hard terms. It was years before ATI admitted to the presence of the vec4 ADD unit in the R3xx-and-up ALU pipeline...

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Old 30-Apr-2007, 17:42   #3858
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Originally Posted by oeLangOetan View Post
The fat alu is probably the special function unit
that's for sure, but since they just mention "integer and logic ops support" it makes me think
that thesere ops are not orthogonal to any ALU. I might be wrong of course.
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Old 30-Apr-2007, 17:46   #3859
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Well, the specs certainly look very yummy! And close to what Jawed and I originally speculated about! Only with a lot stricter scheduling.

So, it does seem to be a case of bad drivers, after all. If it delivers, it should surely dethrone the 8800 easily.


I think they have hidden a large operand cache on the chip, to store all those VLIW ops. Think about it: they need something in the order of a 128 bit word each clock for each ALU simply to keep it going.
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Old 30-Apr-2007, 17:52   #3860
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Since when is it possible to transmit digital audio via a DVI connector? Surely part of the reason HDMI exists at all is precisely that it adds to DVI the ability to transmit video and audio down the same cable?
Higher bandwidth and mandatory HDCP (over HDMI) support are some others that come to mind.
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Old 30-Apr-2007, 17:57   #3861
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Higher bandwidth and mandatory HDCP (over HDMI) support are some others that come to mind.
I did say part of the reason ; there are lots of other factors: resilience of signal is another (can be quite hard work getting DVI to work over a 10-metre cable, but not too tough with HDMI). But mao was claiming that R600 would output audio via DVI (and hence into an HDMI cable via a dongle); I wasn't aware that was possible.
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Old 30-Apr-2007, 18:00   #3862
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Higher bandwidth and mandatory HDCP (over HDMI) support are some others that come to mind.
Technically HDMI does not mandate HDCP, just that the likely implementations means they will nearly always go hand in hand.
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Old 30-Apr-2007, 18:11   #3863
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Well, the specs certainly look very yummy! And close to what Jawed and I originally speculated about! Only with a lot stricter scheduling.
Well, for me, thread packing was a big step beyond this, aimed at improving branching at the same time as throughput. R3xx...R5xx can issue 4 ALU instructions per clock (I think; at least 3).

Quote:
So, it does seem to be a case of bad drivers, after all. If it delivers, it should surely dethrone the 8800 easily.
I think it's really the case that most DX9 games (that are capable of stretching G80/R600) are ROP or TMU limited (turn on all the shadows and make the trees look high res). I'm really doubtful we'll see much advantage for R600 due solely to ALU instruction throughput.

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I think they have hidden a large operand cache on the chip, to store all those VLIW ops.
Confused, do you mean instruction cache?

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Think about it: they need something in the order of a 128 bit word each clock for each ALU simply to keep it going.
I'm struggling to see how this is markedly different from R3xx or NV4x (or NV3x). Aren't these all VLIW processors? Don't forget the texture instructions too. Ooh, and the vertex fetches. And memory reads/writes (gather/scatter)?

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Old 30-Apr-2007, 18:19   #3864
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Originally Posted by nicolasb View Post
I did say part of the reason ; there are lots of other factors: resilience of signal is another (can be quite hard work getting DVI to work over a 10-metre cable, but not too tough with HDMI). But mao was claiming that R600 would output audio via DVI (and hence into an HDMI cable via a dongle); I wasn't aware that was possible.
How about using the analog pins on the DVI along with a proprietary dongle to send the audio? They should have enough bandwidth to carry the signal, and aren't being used when it's sending digital video.
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Old 30-Apr-2007, 18:22   #3865
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The last shot of the ring-bus isn't showing any different in the topology, compared to the R500 line, as the earlier slides stated -- just the doubled internal and external data channels.

So, R600 seems to be a scalar outfit, just like G80, but with rather different structural stacking.
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Old 30-Apr-2007, 18:30   #3866
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Originally Posted by Kaotik View Post
The last doesn't seem official as the rest, wasn't the general impression that it has 16x32bit, not 8x64bit controllers?
Hmm, both GDDR3/4 can be arranged as 16Mx32bit (8banksx2M)=512Mbit/8=64bit. The relationship between ring-stops/controller width hasn't been disclosed (AFAICR). The final pic indicates 8x64bit channels as per the 3,3,2 layout of DRAMS on the PCB. It also suggests that memories can share a channel, so back to back mounting lines up with 2900XT board pics. Of course it could also be expediancy of layout.
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Old 30-Apr-2007, 18:34   #3867
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Well, for me, thread packing was a big step beyond this, aimed at improving branching at the same time as throughput. R3xx...R5xx can issue 4 ALU instructions per clock (I think; at least 3).
Agreed.

Quote:
I think it's really the case that most DX9 games (that are capable of stretching G80/R600) are ROP or TMU limited (turn on all the shadows and make the trees look high res). I'm really doubtful we'll see much advantage for R600 due solely to ALU instruction throughput.
That might be the case. But then again, the preformance hit from better filtering would be reduced, and it makes sense to do preprocessing through the vertex shaders that would be too costly in the past. Less shading for the pixelshaders as well.

Quote:
Confused, do you mean instruction cache?
Yes, sorry.

Quote:
I'm struggling to see how this is markedly different from R3xx or NV4x (or NV3x). Aren't these all VLIW processors? Don't forget the texture instructions too. Ooh, and the vertex fetches. And memory reads/writes (gather/scatter)?
Yes, but you have many more ALUs, that can do more things as well. As they're scalar, that alone increases the amount of instructions needed five times. And there are L1 and L2 caches for those other things as well.

And while a ringbus is really neat, it does require a lot of additional buffers as well, including a good scheduling mechanism that needs to be aware of the data required plenty in advance. Switching to a different thread is no solution either, because that requires a data refresh as well.
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Old 30-Apr-2007, 18:55   #3868
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This stuff is getting more and more over my head. I'm curious on how hardocp interpret it.
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Old 30-Apr-2007, 18:56   #3869
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This stuff is getting more and more over my head. I'm curious on how hardocp interpret it.
Probably the same way you did.
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Old 30-Apr-2007, 18:59   #3870
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Originally Posted by fellix View Post
The last shot of the ring-bus isn't showing any different in the topology, compared to the R500 line, as the earlier slides stated -- just the doubled internal and external data channels.
This previous slide indicates some differences as x1k design used an internal switch/x-bar. I guess the exact topology is unknown.
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Old 30-Apr-2007, 19:02   #3871
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Probably the same way you did.


I need a 3D for dummies book now.

And the r/v6x0 series supporting pcf, does this mean those complaints about shadows not rendering right will go away?
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Old 30-Apr-2007, 19:05   #3872
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Originally Posted by wishiknew View Post


I need a 3D for dummies book now.
You might be better off with a "CPUs and distributed computing for dummies" book, as that's more or less what the GPUs are becoming.

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Old 30-Apr-2007, 19:17   #3873
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Old 30-Apr-2007, 19:18   #3874
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Originally Posted by tertsi View Post
R600XT (co-issue 3 instructions) - 93,9277 GInstr/sec

8800 GTX - 39,1998 GInstr/sec
Those numbers seem to indicate that not only is R600 faster than G80 but it's also more efficient in terms of ALU usage. That's puzzling since R600's max theoretical advantage is ~ 40% assuming perfect utilization and ignoring G80's MUL.

tertsi, what are the theoretical maximums for instruction throughput on this test given what you know of G80 and R600?
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Old 30-Apr-2007, 19:18   #3875
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Additional slides about AA on R6xx... (Posted at Xtremesystems)





Jawed, you're the man!! You are right on a tent filter!!

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Originally Posted by Jawed
Good summary.

The blur should be mitigated by the use of a tent filter, which looks like /\ across the width of a pixel, instead of the classic box. The samples outside of the pixel will be weighted lower than those inside. What we can't tell, as yet, is how granular the weightings are, whether it's a tent based on radius for all samples, or a tent for only those samples outside the pixel based on distance, or a simple fractional weighting based on the fact the samples are outside the pixel.

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