[Geo]

Some history
The ATI R600 Rumours & Speculation Centrum
The (inappropriately named) LAST R600 Rumours & Speculation Thread
Huddy says R600
Xbit: This report is the standard for where "64 shaders" comes from.
B3D on 80nm.
B3D on 512-bit to external memory
B3D on Xenos heritage
Tech Report suggesting Dave Orton said "96 shaders" for R600. However, actual quote was "next generation", which might leave the door open that he was referring to a 65nm refresh rather than R600.
Roughly 6 pages of talking about reported claimed die shots starting at #674 here
Site claiming to have an R600 listing specs and "testing" results. Sober and considered opinion of B3D staff concerning the claimed specs: "Pttthhhppptt!"
DailyTech finding said site credible.
CJ's leaked specs discussing timeframes, prices and performance estimations on this very thread.
Henri Richard promises Q1 for R600 launch
AMD sets Tech Day for R600
Beyond3D and Xbit report R600 pushed to Q2.

Some spec and launch date information from the AMD 690G launch on 2/28/2007.

[Arty]

The interesting bits from that EETimes article:

• Separately, AMD gave one of the first public demos of the R600, its next-generation graphics controller that uses 320 multiply-accumulate units.
• The company showed a Barcelona-based system using two 200W R600 graphics cards to hit a terabit/second benchmark.
• AMD also demonstrated working versions of its next-generation graphics chip the R600 to be released by the end of June.
• Release of the R600 has been delayed "a few weeks" so that AMD can roll out a full suite of graphics chips covering multiple market segments for the latest Microsoft DirectX 10 applications programming interface.

[Farhan]

It's teraflop, not terabit

http://www.reghardware.co.uk/2007/02...d_690g_launch/
http://www.informationweek.com/news/...=Breaking+News
http://blogs.zdnet.com/Berlind/?p=363
http://content.zdnet.com/2346-10741_22-57089.html
http://blogs.zdnet.com/Berlind/?p=364

http://www.boincstats.com/stats/host...sah&st=0&or=10 - zomg Barcelona?

[R300King!]

Why the new thread?

AMD gave one of the first public demos of the R600, its next-generation graphics controller that uses 320 multiply-accumulate units. The company showed a Barcelona-based system using two 200W R600 graphics cards to hit a terabit/second benchmark.

So doesn't this mean it's 320/2 = 160 units? If you divide the 160 by vec4 you get 40.

But not sure if any of this is even true.

[INKster]

Originally Posted by R300King!

So doesn't this mean it's 320/2 = 160 units? If you divide the 160 by vec4 you get 40.

But not sure if any of this is even true.

And if you multiply 40 by 2, you get 80.

[R300King!]

Also, that 1 Terabit(is that correct?)/sec processing power, does that include the CPUs?

The company showed a Barcelona-based system using two 200W R600 graphics cards to hit a terabit/second benchmark

[R300King!]

Originally Posted by INKster

And if you multiply 40 by 2, you get 80.

Yeah, I know. I mean a single R600 chip will only have 160 or 40 vec4. Maybe that board was with 2 mid-range R600s with few shaders than the XTX version. Who knows?



OT Have you seen Level505 recently, it's covered with ads. Way more than before. lol

[Jawed]

Aha, Barcelona/R600

Jawed

[SirPauly]

Separately, AMD gave one of the first public demos of the R600, its next-generation graphics controller that uses 320 multiply-accumulate units. The company showed a Barcelona-based system using two 200W R600 graphics cards to hit a terabit/second benchmark.

Release of the R600 has been delayed "a few weeks" so that AMD can roll out a full suite of graphics chips covering multiple market segments for the latest Microsoft DirectX 10 applications programming interface. Rival Nvidia rolled out its high-end DX10 graphics controller, the GeForce 8800 last fall but has not filled out its product line with midrange and low-end parts based on it yet.

"As soon as AMD makes their DX10 announcements, I am sure we will hear about competing products from Nvidia," said McCarron.

In addition, AMD announced a new desktop chip set, the first from the ATI division since the merger last fall. The AMD 690 sports an ATI Radeon X1250 graphics core and a new video decode block. It is also the former ATI's first chip set to support the HDMI video interface with HDCP copy protection for high definition video.

Good news.

[SirPauly]

So does 320 Multiply Accumulate units = 80 shaders?

[Sound_Card]

Just when I was in a down mood with all this bad news of R600 springing up, this stuff pops up and smacks me in the face.

So Indeed, AMD is going for a complete platform launch.

[Natoma]

Originally Posted by SirPauly

So does 320 Multiply Accumulate units = 80 shaders?

Geo is collecting his wager winnings.

[Sound_Card]

Originally Posted by SirPauly

So does 320 Multiply Accumulate units = 80 shaders?

It could be some hybrid form me thinks. Like 160 scaler shaders and 40vec4. Or I could be dead wrong and dumb.

[Razor1]

well if its vec4+scalar, so that would be 64 units if its vec 3 + scalar then 80 units, at least thats what it sounds like to me.

[Sound_Card]

Originally Posted by Razor1

well if its vec4+scalar, so that would be 64 units if its vec 3 + scalar then 80 units, at least thats what it sounds like to me.

64vec4+scaler sounds very good to me.

[Cuthalu]

So, what's the realease date gonna be; "a few weeks" + "by the end of June" = release in April, and June referring to the ending of Q2 which was the final possible date of previous Q2-timewindow?

[Geo]

http://www.beyond3d.com/#news39176

The bit about early rumors would be a reference to both Xbit reporting 64 shaders and ATI (at the time) reporting that they'd leveraged Xenos. Add in todays 320 and some "version 2" of unified hints, and you've got the reasoning we used for that last bit.

[Sound_Card]

Originally Posted by Cuthalu

So, what's the realease date gonna be; "a few weeks" + "by the end of June" = release in April, and June referring to the ending of Q2 which was the final possible date of previous Q2-timewindow?

I though that "delay of a few weeks" was refering to cebit.

[pakotlar]

Originally Posted by Geo

http://www.beyond3d.com/#news39176

The bit about early rumors would be a reference to both Xbit reporting 64 shaders and ATI (at the time) reporting that they'd leveraged Xenos. Add in todays 320 and some "version 2" of unified hints, and you've got the reasoning we used for that last bit.

geo that would be pretty exciting if true. 64 vec4 + scalar wouldn't be too shabby at all if the arbiter was decently efficient.

edit: Am i missing something? What happened to plain old 80vec4? I didn't read the EEtimes article. Maybe I should check that.

[Geo]

Originally Posted by Cuthalu

So, what's the realease date gonna be; "a few weeks" + "by the end of June" = release in April, and June referring to the ending of Q2 which was the final possible date of previous Q2-timewindow?

I don't think we heard anything today to change the opinion we offered on the front page last week that we're probably looking at late April or early May.

[Cuthalu]

What's the difference between vec4 + scalar and vec4? Is it better to have 64 vec4 + scalar than having 80 vec4, and if so, why?

[Geo]

Well, that they are referring to "320" would suggest that they might be all functionally scalar, even tho grouped as 64 5D (our guess) or 80 4D (certainly not impossible). To the degree the scheduling allows them to be treated as scalar, then which it is won't be all that important for most purposes. Scalar at all is the big thing, as vec4 will not be as efficient (tho you could get a lively argument going about how much control logic you have to add to make that happen in calculating the relative efficiency).

[Pete]

Once again, Geo, I didn't think before posting. Vec4 + scalar lines up with Xenos, so 64 sounds right. A little harder to line up against G80, perhaps, with that rogue scalar, but it'll be an interesting fight, for sure.

(That scalar also makes for a nice "+25%" on top of 64 vec4s. Now, where have I heard "+25%" before? Am I just spinning my brain cells if I think of preemptive PR? )

But functionally scalar, eh? That'd be a kick in the pants. I wonder if their unified v.2 would take that step.

Anywho, if Xbit was right about 64 shader units, then they're probably right about 16 texture units, and that may mean 16 ROPs. But 16 of NV's, or something more? It'd almost have to be more, seemingly, given all that bandwidth and if we can estimate the shader and so core clock from the 2 * R600 = teraflop figure.

[Geo]

What I want to see is if rwolf can make 320 ALUs and 500 mflops into something 2GHz-ish.

[psurge]

Geo - easy. They could operate at 2.4GHz but only have throughput of 1 madd every 3 cycles.