[The_Wolf_Who_Cried_Boy]

I thought about posting this in the R600 Rumor thread but it seemed it might be a bit disruptive.

Originally Posted by The Inquirer

People forget that the number of metal layers is also increasing, so allowing additional hundred million or so transistors to be packed in.

Admittedly I have a similar grasp of circuit design as toads do of quasars, but, arn't transistors formed in the bottom layers of polysilicon, with the the lowest layers of metal interconnect linking the transistors together to form logic/ SRAM/ whatever, with the progressively higher levels of interconnect providing ever more global linkage?

Does increasing metalization layers have a direct impact on transistor density?

[Skrying]

I can't answer your question, but I believe I read something about Intel using what sounded like a similar method for some future chips.

[AlStrong]

They may be referring to double gated transistors, which can better deal with leakage.

(maybe...)

[silent_guy]

Originally Posted by The_Wolf_Who_Cried_Boy

Admittedly I have a similar grasp of circuit design as toads do of quasars, but, arn't transistors formed in the bottom layers of polysilicon, with the the lowest layers of metal interconnect linking the transistors together to form logic/ SRAM/ whatever, with the progressively higher levels of interconnect providing ever more global linkage?

Does increasing metalization layers have a direct impact on transistor density?

Yes, that's correct. But one of the big problems when layouting chips is interconnecting all those transistors. There are 2 steps in this: the transistors themselves are interconnected to form logical gates and packaged into standard cells. The interconnection of those transistors happens in metal 1 and this is fixed for a standard cell: it's part of the standard cell library and it's not touched.
The other metal layers are then used to interconnect those standard cells.

In 90nm, the typical, so called, utilization factor is roughly around 75%, with a large variance around that. This means that 25% of the area is not covered with standard cell and thus basically wasted (utilization factors are only calculated for area that's not covered with RAM). The reason for this is routing density: if you have logic that has a lot of global interconnection, your metal layers simply are not enough to connect everything together.

This is why additional metal layers can help.

That said, there are diminishing returns: the higher your metal layer, the lower the density. In a 90nm process, M1 can have feature sizes that are roughly the same size as transistors. (E.g. metal wires roughly as wide as transistors.). As you go up, the feature size increases steadily, so the wire density drops.

More metal layers are also significantly more costly: for smaller chips, it's often cheaper to increase the die size a bit (lower utilization factor) in return for 1 or 2 less metal layers.

[The_Wolf_Who_Cried_Boy]

Thanks for responses.

Originally Posted by silent_guy

In 90nm, the typical, so called, utilization factor is roughly around 75%, with a large variance around that. This means that 25% of the area is not covered with standard cell and thus basically wasted (utilization factors are only calculated for area that's not covered with RAM). The reason for this is routing density: if you have logic that has a lot of global interconnection, your metal layers simply are not enough to connect everything together.

Would this be one main reason why AMD seem to use 2-3 additional layers for a given process node relative to Intel? Both being limited in fab capacity and SOI being innately more expensive the additional layers at least allow maximum utilization of available die area?

[Jawed]

So I guess this is where the X Architecture that ATI licensed comes in?

http://www.beyond3d.com/forum/showthread.php?t=20813
http://www.beyond3d.com/forum/showthread.php?t=23144

If X Architecture saves a metal layer, then you can use that metal layer for something else

So it originally debuted on 110nm for ATI and it's also available on 90nm. Is it also available on 80nm?

Jawed

[silent_guy]

Originally Posted by Jawed

So I guess this is where the X Architecture that ATI licensed comes in?

Yes, absolutely.

http://www.beyond3d.com/forum/showthread.php?t=20813
http://www.beyond3d.com/forum/showthread.php?t=23144

If X Architecture saves a metal layer, then you can use that metal layer for something else

So it originally debuted on 110nm for ATI and it's also available on 90nm. Is it also available on 80nm?

The X architecture was pitched to my company about 5 years ago. But a lot of pieces of the puzzle need to fall in place, so while interesting, we never considered it. The company was then bought by Cadence and I thought the technology had died a untimely dead.
The problem is that software and hardware tools need to be adapted for it in non-trivial ways: most algorithms are simplified a whole lot by assuming only Manhattan routing.

Very interesting to see that somebody actually uses it. I didn't know that.

Once the tools are in place for 90nm, I don't see why it wouldn't work for 80nm.

[silent_guy]

Originally Posted by The_Wolf_Who_Cried_Boy

Would this be one main reason why AMD seem to use 2-3 additional layers for a given process node relative to Intel? Both being limited in fab capacity and SOI being innately more expensive the additional layers at least allow maximum utilization of available die area?

That could be one of the reasons. But there could also be others: Intel typically has a higher full custom/std. cell ratio. Std. cells always give lower utilization rates. That's even more so for automatically places std. cells. Another possibility is that Intel simply has a better methodology: Only a few companies has the size to support their own large in-house R&D facilities. Intel is one of them. IBM too(*). I doubt AMD has it. That's not to say Intel doesn't use off-the-shelve back-end tools, but there's a lot of black magic in there and if you can afford 20 engineers working only on utilization improvement, you really can make a difference. And maybe the upper metal layers of the Intel process have a higher density than the one of AMD? That would also make a big difference.

(*) They have really cool names for their own tools: static timing analysis with Einstimer. Logic synthesis with Booldozer. etc. How more inspired than 'Design Compiler'.