[Nappe1]

well, I have been looking some tests to see how this 2-year-old Low End Chip from SiS can keep up against it's competitors and found some earliest ones which showed totally awfull performance and lot's of troubles with drivers.

then I found this one from xbitlabs: http://www.xbitlabs.com/video/sis315/
which looks like a good review. It shows the problems that chip has but still finds some good sides from it.

Then I went to the MadOnion's database to look for some benchmark results and find a fastest one with 64MB SiS315: http://service.madonion.com/compare?2k1=1988917
...And compared against my system. I was shocked! SiS has really made a progress with their drivers. Just look at the following picture:

SIS 315 64MB on 1.4Ghz Thunderbird vs. ATi All-In-Wonder Radeon 32MB DDR (166Mhz/166Mhz DDR) on 1Ghz Thunderbird


and if you look the overall score, it doesn't looks so good, but then, that thing is practically as fast as my year old High End card in some tests.

So it looks like those SiS 33x tests are something really to wait for.

[Tagrineth]

Wow. That's pretty impressive! SiS could really have something going here.

[Ailuros]

Well if that graph is set as a comparison, I don't see any comparable cpu speeds for one; and no 400mhz difference is nothing to sneeze over, nor is 3dmark2001 cpu independant.

Hardware T&L? errrrrrrr ok......

[Hyp-X]

But the Athlon 1.4 had a 66MHz FSB :P

[CHHAS]

I think that's a 3Dmark2002 bug with the SIS645 chipset, my Athlon 1200 is displayed as having a 66 MHz FSB as well.

[OVERLORD]

This gets even more interesting. Another tiler. Wouldn't it be interesting if they implement t&l and ddr?

From http://www.ocworkbench.com/index.stm

Gzeasy's SIS330 8x AGP technical queries
Posted by overclocker at 90

Below is a translation of the Q&A of Gzeasy.com

GZeasy.comF Does SIS330 supports Vertex Shader and Pixel Shader ?
SiSFSIS330 does not support Vertex Shader but supports Pixel Shader.

GZeasy.comFSiS330 supports which version of Pixel Shader ? 1.1, 1.3 or 1.4 ?
SiS : SiS330 supports version 1.3 of Pixel Shader.

GZeasy.comF Does SIS330 uses Tiled Based Rendering or Hierarchical Z?
SiSFYes, it is based on Tiled Based Rendering.

GZeasy.comFDoes SIS330 supports an improved bandwith e.g. Z-compression, fast z-clear ?
SiSFSIS330 supports Fast Z-clear.

GZeasy.comFHow many transistors are there on SiS336 ?
SiSFSiS336 has 30million.

GZeasy.comFHow many Research engineers are there in the team ?
SiSFThere are around 200 persons involved in the R&D of SiS330. This includes research in Software and Hardware.

http://www.gzeasy.com/itnewsdetail.asp?nID=2342

[nAo]

Umh..very interesting. Now, I DO want to see some benchmark

[Idiot]

why would you need Z-clear when you got a tiler???

BTW it also says that it can do 4 textures on a pixel in a single pass as well. not 8...

[Humus]

I suppose it's just tiling the buffers, but isn't a deferred renderer.

[nAo]

Originally Posted by Humus

I suppose it's just tiling the buffers, but isn't a deferred renderer.

The term 'TBR' is certainly ambiguous, but the question:

Does SIS330 uses Tiled Based Rendering or Hierarchical Z?

it's not. It places a question on visibility subsystem, IMHO.

ciao,
Marco

[nAo]

Originally Posted by Idiot

why would you need Z-clear when you got a tiler???

The hw have still to clear the internal zbuffer when it starts to render after the binning stage. Obviously having a fast z-clear is a direct advantage on a TBR.

BTW it also says that it can do 4 textures on a pixel in a single pass as well. not 8...

?? it is not a rule to have 8 textures per pass on TBR

ciao,
Marco

[OVERLORD]

[Idiot]

nAo: thx, so maybe they say they have fast z clear per the virtue of TBR (if they are using TBR) or something.

Oh, and the last part is just something that oc bench didn't translate, and yeah i know it says nothing about TBR, but its one of the limitation publicly disclosed.

[nAo]

Originally Posted by Idiot

nAo: thx, so maybe they say they have fast z clear per the virtue of TBR (if they are using TBR) or something.

Yeah, a good TBR would clear the zbuffer while dumping the rendered tile on the external memory, thus completely hiding the z-buffer clear

Oh, and the last part is just something that oc bench didn't translate, and yeah i know it says nothing about TBR, but its one of the limitation publicly disclosed.

Could u translate it for us?

[Idiot]

First since my ability to read "technical" chinese is pretty bad, this piece would be better translated by Pcchen, Rookie, or Anton 9the owner of gzeasy) not to mention my knowledge about graphics matters SUX.

The missing parts are

Gzeasy: How do you achieve single pass 8 texuring? Do you do it in 2 pipelines in 4 cycles? or Do you do it in 4 pipelines in 2 cycles?
SiS: 330 have 4 pipelines each with 2 TMU. SiS330's pipelines can support single pass quad texuring (2 cycles).

(i might have the "cycle" or "pass" wrong, because I really aren't sure what exatly do they mean by those chinese)

GZeasy.com：How many Enginners are in the SiS330 development Team?
SiS：Including both hardware and software, there are about 200 people who are involved with SiS330's development.



Hope I have not violated Anton's copyrights.....

[Teasy]

SIS3xx series a TBR?.. nah its performance isn't anywhere near high enough from what I've seen. Its performance seems more like a standard 4 piped IMR with standard DDR ram and the usual bandwidth saving tech and very early drivers.

[nAo]

Are there any SIS3xx benchmarks around on the net?

[Humus]

I don't think so, but they did at least put out some numbers on some slide, showing a 3dmarks score of above 5000 at least. I'd think performance will improve too, it's still early drivers and silicon.

[cho]

Hi , here is the original text in the reply from SiS ( i translate them into Chinese , and OCworkbench re-translate the Chinese to English ):

1. SiS336 have SW Vertex Shader, no HW Vertex Shader
SiS336 have HW Pixel Shader

2. SiS336 support HW Ver 1.3 Pixel Shader

3. Yes, HSR by tile removal algorithm.

4. SiS336 have fast Z Clear

5. SiS336 have about 30 million transistors

6. There are total 8 texture unites and 4 pixel pipelines in SiS336.
Each pixel pipeline have 2 texture unites.

Sis336 hardware can support maximum 4 texture rendering for
each pipeline.(with 2 times loop)

7. Above 200 HW+SW RD join 336 project.

[nAo]

Originally Posted by cho

3. Yes, HSR by tile removal algorithm.

This answer is unclear. Please, can u post the original question?
Better...can u ask them a more detailed question?
Something like:
Does SiS3xx collect all the scene in memory? and then does it proceed to render all the scene on a per tile basis?
On in another words: is SiS3xx an immediate mode renderer or a deferred renderer?
Ok..maybe I'm asking to much, thanks anyway

[ram]

Originally Posted by cho

3. Yes, HSR by tile removal algorithm.

I would say this is a confusing way to explain that it does hierarchical Z.