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#1 |
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Senior Member
Join Date: Jul 2002
Posts: 2,177
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With the R6xx apparently using alot of the Xenos features .. what will ATI have to do to make the R6xx SM4.0 compliant since Xenos is not fully SM4.0 compliant?
Thx US
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God put me on earth to do a certain number of things. Right now i'm so far behind that i'll never die. Random 512Kb onboard -> S3 Virge 4MB -> RivaTNT2 -> GeforcePro -> GF3 -> NV3x -> R420 -> R580 -> G80 -> G92 -> 5870 -> ??? |
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#2 |
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Off-season
Join Date: Feb 2002
Location: On the pursuit of happiness
Posts: 3,019
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That's difficult to say since we don't know exactly what's supported at the hardware level. Some things could be broken down do simpler instructions, while others would be horribly expensive. I guess ATI would need to add special number handling, 32bit integer support, texture arrays, texture addressing with offset, SampleCmp, sRGB correction before filtering and probably instance/primitive/vertex ID.
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Binary prefixes for bits and bytes |
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#3 |
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Member
Join Date: Oct 2004
Location: South Coast, England
Posts: 391
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Wonder if they'll try and cheat their way into a "D3D10 Compatable" release. Like they did with vertex texturing/SM3/X1k's
Jack |
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#4 | |
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Senior Member
Join Date: Jul 2002
Posts: 2,177
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Thx for your guess Xmas.
Quote:
I wonder how many more transistors the R6xx will have over Xenos .. since they'll need to fix the chip for SM4.0 compatibility. With the R580 being around 384 Million .. what would a good figure be for the R6xx? R420 Million? US
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God put me on earth to do a certain number of things. Right now i'm so far behind that i'll never die. Random 512Kb onboard -> S3 Virge 4MB -> RivaTNT2 -> GeforcePro -> GF3 -> NV3x -> R420 -> R580 -> G80 -> G92 -> 5870 -> ??? |
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#5 |
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Senior Member
Join Date: May 2005
Posts: 2,038
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I think we could await more ALUs (or "unified shader units"). R580 has 48 units for pixel shading and 8 units for vertex shading (=56 total). Xenos has 48 units enabled (total). I don't await anything less than 64 units for R600. And I think that even 96 isn't excessive number... Xenos is very small on 90nm, so there should be a lot of die-space to use @80nm/65nm (my theory, don't bite me please).
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Sorry for my English. But I hope it's better than your Czech |
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#6 | |
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Senior Member
Join Date: Jul 2005
Location: State of Illusionism
Posts: 2,091
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Quote:
This shouldnt happen anymore in order for any company to call their cards "Fully WGF2.0/DX10 compliant." Microsoft does not want any graphics card company implimenting (excuse my language) half assed versions of direct X like what happened with DX9/DX9C and SM2.0, SM2.0C, SM3.0 etc.. as well as PS1.1/1.4 way back when. It benefits nobody and makes much of the work the Direct X team does totally useless if manufacturers can skip support for key features or basic functions/support. Also plays problems with game developers with what to support for a certain userbase. Technically both companies will need to support all features of any given DX version (dictated by MS) to be called fully compatible/compliant. Starting with vista we should see no variation in what any company supports within the DX versions. Anything that differs will be customizations/optimization of any company seperate of what basic features which any must support. For example under the new rule using SM3.0 and the R520 as an example, ATI would have to support vertex texture fetch, however they can also, in addition, add their own custom render to VB as well and recieve certification. So its a great thing as no matter what card you buy within a given time frame, you will have the key support, and companies have the flexability to add in their own optimizations and custom ways of doing things as well. Last edited by SugarCoat; 25-Feb-2006 at 18:35. |
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#7 | |
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Member
Join Date: Mar 2003
Location: Denmark
Posts: 867
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#8 |
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Senior Member
Join Date: Jul 2002
Posts: 2,177
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How will the 96 shader units be defined? 32Pipes with the 3 ALU's or some other method? Maybe increase the ALU's or something else?
US
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God put me on earth to do a certain number of things. Right now i'm so far behind that i'll never die. Random 512Kb onboard -> S3 Virge 4MB -> RivaTNT2 -> GeforcePro -> GF3 -> NV3x -> R420 -> R580 -> G80 -> G92 -> 5870 -> ??? |
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#9 | |
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Member
Join Date: Mar 2003
Location: Denmark
Posts: 867
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#10 | |
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Senior Member
Join Date: Jul 2005
Location: State of Illusionism
Posts: 2,091
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Quote:
its broken down in shader pipes and operations per cycle (xenos =2 operations per pipe per cycle so 48 pipes @ 2 per pipe per cycle = 96 shader operations per every one cycle in a xenos) and there are also a number of arithmatic logic units per pipe (xenos = 4) which gives the capability to do vertex or pixel. As far as i have seen as well, the Xenos ( and problably R6XX) wont be broken up into quads, but arrays, in the case of Xenos each one of the three working independantly and containing 16 shader pipes. Last edited by SugarCoat; 25-Feb-2006 at 21:01. |
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#11 | |
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Senior Member
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GPU blog |
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#12 | |
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Senior Member
Join Date: Jul 2002
Posts: 2,177
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If the Xenos is not as powerful as the R580 .. yet we expect the R6xx to be even more powerful than the R580 .. what can we expect ATI to do, to increase the R6xx performance over the R580 seeing as they going the Xenos way(maybe).
A higher core clock is one way, a higher memory clock the second. But what can ATI do to add to that? As Tim said .. maybe 128 units instead of 96? Anything else? As for feature wise .. well Xmas added a few. Quote:
US
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God put me on earth to do a certain number of things. Right now i'm so far behind that i'll never die. Random 512Kb onboard -> S3 Virge 4MB -> RivaTNT2 -> GeforcePro -> GF3 -> NV3x -> R420 -> R580 -> G80 -> G92 -> 5870 -> ??? |
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#13 | |
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Stealth Nerd
Join Date: Jul 2003
Location: Sunny Melbourne
Posts: 1,112
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Human Rights [X---------|----------] Robert Menzies |
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#14 | |
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Member
Join Date: Oct 2005
Posts: 331
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Bob Feldstein, vice president of Engineering, ATI Technologies, Inc. "We selected Intrinsity after determining that Fast14 Technology can deliver up to four times the performance per silicon dollar when compared with standard design approaches." There you have it. And with the ArtX design team, they'll surely be able to deliver. Who knows, could be TBDR. /me worships the mysterious Lord "Tech" |
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#15 | |
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Member
Join Date: Oct 2004
Location: South Coast, England
Posts: 391
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Quote:
The only "backdoor" I can think of is that of performance. I've not seen anywhere that requires a certain minimum level of performance. That is, they could enable a feature so that it's compliant - but have it emulated via other features (e.g. for ATI SM2 cards you can do FP blending if you emulate it via a post-processing pass given that the hardware doesn't natively allow it). This leaves the possibility that the feature might technically work, but it's so damn slow that it's just not worth using it. Which as far as I see it isn't far off not having supported the feature in the first place However, as the IHV's now have to compete on performance rather than features - so I doubt it'll be a problem. Time will tell though. Cheers, Jack |
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#16 |
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Senior Member
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Yes, “Software Emulation“ could be the next big fear in the Direct3D developer camp. But IMHO running slow is still better than not running at all.
I have seen some performance requirements that need to be meet to get a Vista Logo. But they seem not very high. Maybe WinSat can help a little bit.
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GPU blog |
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#17 | |
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Regular
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As far as I can tell Xenos supports texture arrays:
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Is that a texture array? Does D3D10 go further? Jawed |
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#18 |
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Senior Member
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Yes this is comparable to texture arrays in D3D10. If I understand the constant values in D3D10.h right an array can contain up to 512 textures.
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GPU blog |
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#19 | |
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Off-season
Join Date: Feb 2002
Location: On the pursuit of happiness
Posts: 3,019
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Quote:
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Binary prefixes for bits and bytes |
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#20 | |
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Senior Member
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GPU blog |
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#21 |
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Casual Member
Join Date: Feb 2002
Location: switzerland
Posts: 2,088
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I think this question fits in this thread
What are some of the requirements of d3d10 for texture formats and filtering and blending? I heard fp32 blending is required. depth stencil format is. 32bit z-buffer maybe? fp16 filtering yes or no , fp32 is optional i know Is MSAA gonna be a requirement?
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f@h name griswoold |
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#22 |
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Mostly Harmless
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http://www.elitebastards.com/forum/v...5f1230f#192764
Here's another "wise guy" rejecting "R600" as the name. Should we just go ahead and agree on "R620" now then and get it out of the way?
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"We'll thrash them --absolutely thrash them."--Richard Huddy on Larrabee "Our multi-decade old 3D graphics rendering architecture that's based on a rasterization approach is no longer scalable and suitable for the demands of the future." --Pat Gelsinger, Intel ". . .its taking us longer than we would have liked to get a [Crossfire game] profiling system out there" --Terry Makedon, ATI, July 2006 "Christ, this is Beyond3D; just get rid of any f**ker talking about patterned chihuahuas! Can the dog write GLSL? No. Then it can f**k off." --Da Boss |
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#23 | |
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Naughty Boy!
Join Date: Jan 2006
Posts: 472
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Quote:
Exactly how useful those mini-ALU's are in relation to the full ATI ALU's is an exercise in futility. Believe me I've tried. But 64 "full" ALU's in R580 in R600 might possibly equal R580..though I strongly doubt it. My bet would be 96.. |
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#24 |
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Senior Member
Join Date: May 2002
Posts: 4,308
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<dreams of 128 ALUs in R600 with redundancy, with being 96 active>
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#25 | |
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Senior Member
Join Date: Jul 2005
Location: State of Illusionism
Posts: 2,091
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Quote:
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Everything's Eventual Oedipus On The Orpheum Circuit! |
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