[Dave Baumann]

As we reported, during ATI's recent financial conference call ATI noted that R520's release has been moved from "early summer" to "late summer", suggesting that the bring-up of the part hasn't gone as smoothly as they would have hoped. Digitimes is today reporting that R520 is suffering from "leaking issues". Leakage issues within a chip are typically a result of current being used even though a circuit may be disabled, which can result in lower performance than the limits of the process would indicate. R520's have been seen to be operational in a number of circumstances, including running game demonstrations at E3, and seemingly some developers are running them given that game R520 specific game patches have been appearing, suggesting that there is nothing wrong with the functional operation of the chip.

Also in line with some of the statements from ATI, Digitimes reports that ATI may release the mainstream RV530 and entry-level RV515 eahead of schedule and if this were some of them may be announced at the same time as R520. RV530 and RV515 are also expected to utilise the 90nm process, however if they are ahead of schedule it would seem as though these smaller chips may not be suffering similar issues as R520.

[tEd]

Can't they use duct tape to stop the leaking?

[Geo]

How old is that info tho?

We are now back on track, so stay tuned as we get prepared to take the definition of ‘performance leadership’ to a whole new level.

And why wouldn't this impact R500, which they've been nearly giddy about process and yields? Does it get worse as you crank clocks?

[tEd]

higher clockspeed + leakage means (even)more volt , and eventually heat becomes a problem and you can't reach your mhz target.

[digitalwanderer]

Is leakage fixed by a process fix or respin?

[Mariner]

Isn't current leakage process-specific eg. Intel's Preshott?

If this is the case (and if I'm not talking out my arse), surely ATI would have known potential problems with TSMC's 0.09 process well in advance? Doesn't the Low-k thingy help reduce leakage? :?

[nelg]

Originally Posted by digitalwanderer

Is leakage fixed by a process fix or respin?

Diapers.

[banksie]

Originally Posted by digitalwanderer

Is leakage fixed by a process fix or respin?

As I understand it, generally a respin involving shifting functional units physicly to get a little more space between them to prevent current leak across. You can also, if the unit has very well defined switching patterns, interleave functional units so that no adjacent ones are active.

What this probably means is that the lower clockspeed parts are all good to go now. What is busting ATi's plans right now is getting the high-performance parts right. Orton's comments in the conference call seems to indicate that they have cracked this nut recently enough so should now be shifting over to proper production.

[Richard]

How viable is it for ATi/nVidia to go for SOI? And how about a fab?

[jpr27]

Is ATI using the Fast14 process to assist in the development with the 520? Im just wondering because if they did then it could be a problem with Fast14 :? (which I know they were counting on to help with future GPU development and layouts). I could be wrong though because I thought ATI wouldnt start using the Fast14 tech until the R6xx generation

Anyone have info about this or confirm (or deny) if Fast14 was used in the 520? Is the Fast14 still in ATI's future (the R6xx I thought) or later?

[BrynS]

I'm a bit intrigued as to why Digitimes, which seems to have impeccable sources, is only revealing the leakage issue now (which I don't believe they've mentioned when reporting on R520 before) and not earlier in the year, say pre-April timeframe, when it would presumably have surfaced as a problem for ATI, if the current target release is still "late summer."

On the bright side, if ATI can release the whole R(V)5xx family simultaneously or within a few weeks of one another, it should be good news for consumers and perhaps a first in the industry -- the closest I can recall to launching a complete family of products was probably the GeForce 4 launch, but even then, wasn't the GeForce 4(2 )MX series released a month or two later?

Cheers,

BrynS

[digitalwanderer]

Well if they could release a mid-range part that can beat the 7800GTX I think I'll be happy.

[dizietsma]

Personally I think these leakage rumours don't hold any water.

Sorry, that's terrible.

If a mid range Ati even beat X850 then I would be interested as well, that would be very good bang per buck.

With leakage you can still get the performance but you have to pay the price when it comes to thermal issues, considering a graphics card has a lot more transistors and a lot less space for a big heatsink/ fan than a cpu I can see this is where the isue is, and not the actual lack of speed.

If they are suffering from leakage then overclocking might not be great.

[Shtal]

I hope ATI R520 is not going to follow Nvidia NV30 foot_steps

[The_Wolf_Who_Cried_Boy]

Originally Posted by banksie

As I understand it, generally a respin involving shifting functional units physicly to get a little more space between them to prevent current leak across. You can also, if the unit has very well defined switching patterns, interleave functional units so that no adjacent ones are active.

What this probably means is that the lower clockspeed parts are all good to go now. What is busting ATi's plans right now is getting the high-performance parts right. Orton's comments in the conference call seems to indicate that they have cracked this nut recently enough so should now be shifting over to proper production.

Are you sure of that?
Not that I'm an expert on the matter, but isn't a respin optimising the layout of the upper levels of interconnect, rather than modifying the transistor floorplan. Wouldn't the latter require an entire redesign? (IE another $1~2 million for a new mask set).

In regards to Digitalwander, leakage is a fundamental and inescapable problem in transistors that can't be fixed. The problem is the insulation layer in the transistor gate is so thin in <130nm lithography that the current can tunnel through, regardless of wether the transistor is actually on or off. SOI helps a little, but the best means to combat it is use slow switching transistors with large gate widths and thicker layers of insulation. Intel's Dothan notebook CPU is an example, it's manufactured in the same Fabs on the same process as Prescott, but the the balance of leaky fast switching to low-leakage slow switching transistors is reversed.

This page gives the gist of it http://www.techimo.com/articles/index.pl?photo=24

[pat777]

Originally Posted by Shtal

I hope ATI R520 is not going to follow Nvidia NV30 foot_steps

It'll take a lot more than the leakage for the R520 to be an NV30 level disaster.

[Dave Baumann]

Originally Posted by Shogun

Are you sure of that?
Not that I'm an expert on the matter, but isn't a respin optimising the layout of the upper levels of interconnect, rather than modifying the transistor floorplan. Wouldn't the latter require an entire redesign? (IE another $1~2 million for a new mask set).

The bringup process can encompass base, silicon layer changes, as well as metal revisions. Generally speaking you hope that you only need metal revisions as these are generally a little faster, but silicon revisions have happened as well. It sounds to me that much of this may be in the past as the financials already stated they have spent more on R&D over the past quarted to to "increased prototyping costs" for R520 - these would be the new spins of the chip, probably silicon revisions if they are increased from normal levels. The question is how far, if at all, is this news lagging behind the revisions they current have either back now or at the fab at the moment.

[N00b]

Wasn't leakage the reason why Prescott was late and used so much power?
Quoted from an old register article:

Originally Posted by The Register

Leakage has proved something of a problem for Intel's 90nm process following the shift down from 130nm chip production. While smaller transistor ought to consume less power, their more compact size also increases the opportunity for current to leak through, forcing chip makers to up the power in order to get each transistor to operate efficiently.

That's why a 90nm Pentium 4 consumes more power than a 130nm version, not less. However, according to Intel, its 65nm process will "cut leakage by four times at constant performance compared to 90nm transistors", presumably its own ones.

Does not sound unreasonable that ATI has the same problems Intels had. Does anybody know how much power the R520 prototypes draw?

[Jawed]

But AMD didn't have these problems when it moved to 90nm.

Jawed

[trinibwoy]

Originally Posted by Jawed

But AMD didn't have these problems when it moved to 90nm.

Jawed

Much lower clocks? SGOI?

[N00b]

Originally Posted by Jawed

But AMD didn't have these problems when it moved to 90nm.

Jawed

They had problems of their own.

[The_Wolf_Who_Cried_Boy]

Mr Baumann, thankyou for clarifying.

Originally Posted by N00b

Wasn't leakage the reason why Prescott was late and used so much power?

The (mostly) consensus from Real World Tech is not really.

As a frame of reference, Northwood was typical of previous Intel designs in that hundreds (thousands?) of engineers hand tuned the design to within an inch of it's life. Prescott however was designed predominantly using software tools for the layout so as to allow AMD64 compatability in an exceptable time frame. For a given process, a team of talented human engineers will always produce a superior design than software. That, plus it's target clock speeds needing an increase in processing stages bloated it into what we have today. The initial implementation of silicon straining also acted as a thermal insulator preventing proper cooling of early revisions, IIRC this was actually the main delay in it's introduction and the cause of disappointing initial speed bins.
All Intel CPU's are using the same fundamental 90nm process, Prescott is the only one having problems.

[N00b]

Thanks for the explanation Shogun. Is the different layout process why the 90nm Prescott P4s draw as much power as 130nm ones? Or is this leakage-related?

[The_Wolf_Who_Cried_Boy]

Originally Posted by N00b

They had problems of their own.

That artical is putting things to simplistically, and frankly, isn't very good (IMO).
It's as much a question of design methodologies in relation to budgetary constraints more than simply who's process is better.

Risking irony's wrath, simply put, this sums them up.

<IBM------AMD------Intel>

At one end of the spectrum you have IBM who rely very heavily on software layout tools and relatively little on human layout for their CPU designs. This gives them (relatively) quick and low cost development cycles, but, as per my previous response, it doesn't give you optimum performance. The PowerPC achitecture is also IBM's current embedded processor family, and as such they design it for low power consumption at moderate clockspeeds. It is also a sub family of the full blown POWER architecture, IBM's high end performance server CPU. POWER is were the engineers focus, not PowerPC.

At the other end is Intel, again as per my previous response, their methodology is human heavy with a very highly optimised design the result. Prescott is an abberation due to time to market constraints.

In the middle AMD who lack the resources to hand tune like Intel, but do their best. The problem is AMD's first generation of 90nm utilizes 9 layers of wire interconnect, the same as their optimised 130nm, so as to simplify transition between process nodes. Each successive layer of wiring interconnects larger and larger structures, and is tuned for the distance of the signal it needs to carry. The higher the successive layer the larger the diameter of the wire, lowering its capacitance and so allowing the signal to propagate faster. Having had real world experience of 90nm they have now introduced an 11 layer process that is simply better suited for higher speed operation.





appologies for rant...

[Geo]

Originally Posted by dizietsma

If a mid range Ati even beat X850 then I would be interested as well, that would be very good bang per buck.

Ever looked at what a 6600GT does to a 5950U? "Beat" isn't even in the neighborhood of the thrashing it hands out.

It's a lovely thot, but I doubt that ATI was feeling quite that backs-against-the-wall when they built R5xx as NV was when they put together NV4x.