Welcome, Unregistered.

If this is your first visit, be sure to check out the FAQ by clicking the link above. You may have to register before you can post: click the register link above to proceed. To start viewing messages, select the forum that you want to visit from the selection below.

Reply
Old 01-Jun-2005, 17:19   #1
j^aws
Senior Member
 
Join Date: Jun 2004
Posts: 1,908
Default NVIDIA patent: Programmable geometry engine, maybe for RSX?

Quote:
Originally Posted by Patent
User programmable geometry engine

Abstract

A programmable geometry engine is described. One embodiment of the programmable geometry engine includes a programmable primitive engine configured to receive primitive commands that include information for processing vertex data using user-developed programs or subroutines. The programmable primitive engine also is configured to transmit program commands that include program pointers and data pointers. In addition, the programmable geometry engine includes a processing engine configured to receive the program commands. The processing engine is further configured to retrieve the user-developed programs or subroutines using the program pointers and to retrieve vertex data using the data pointers. Also, the processing engine is configured to process the vertex data based on instructions included in the user-developed programs or subroutines to produce processed vertex data and to transmit results to the programmable primitive engine.
...
...
SUMMARY

One embodiment of a programmable geometry engine includes a programmable primitive engine configured to receive primitive commands that include information for processing vertex data using user-developed programs or subroutines. The programmable primitive engine also is configured to transmit program commands that include program pointers and data pointers. In addition, the programmable geometry engine includes a processing engine configured to receive the program commands. The processing engine is further configured to retrieve the user-developed programs or subroutines using the program pointers and to retrieve vertex data using the data pointers. Also, the processing engine is configured to process the vertex data based on instructions included in the user-developed programs or subroutines to produce processed vertex data and to transmit results to the programmable primitive engine.

One advantage of the disclosed programmable geometry engine is that it may be configured to implement specific user-programmed functions. This functionality provides users with the ability to influence a variety of computational parameters and metrics that determine how a graphics processor actually generates primitives in the graphics pipeline. Another advantage is that the disclosed programmable geometry engine has the flexibility to perform vertex operations before and/or after primitive operations. Such flexibility in the architecture enables matrix palette skinning to be performed after tessellation, if so desired. In addition, the programmable geometry engine may include multiple fixed function engines and a scheduler, which arbitrates access to one or more processing engines among the different fixed function engines. The scheduler may be configured to load balance among the different fixed function engines by allowing a fixed function engine with greater processing needs to transmit program commands to the processing engine(s) more frequently than those fixed function engines requiring less processing support. Such load balancing may reduce bottlenecks in the graphics pipeline.
...
User programmable geometry engine

WGF 2.0? PS3's RSX? Or would CELL's SPU's be capable?
j^aws is offline   Reply With Quote
Old 01-Jun-2005, 17:42   #2
nAo
Nutella Nutellae
 
Join Date: Feb 2002
Location: San Francisco
Posts: 4,297
Default

Henry Moreton has filed with NVidia a lot of patents regarding various hw tesselators architectures, I believe there are even more recent patents from him on UPSTO database.
nAo is offline   Reply With Quote
Old 01-Jun-2005, 18:29   #3
cho
Member
 
Join Date: Feb 2002
Posts: 409
Default

geometry shader ?
cho is offline   Reply With Quote
Old 01-Jun-2005, 18:31   #4
version
 
Join Date: Jul 2004
Posts: 452
Send a message via ICQ to version
Default

__________________
Version of Majic12
version is offline   Reply With Quote
Old 01-Jun-2005, 18:56   #5
nAo
Nutella Nutellae
 
Join Date: Feb 2002
Location: San Francisco
Posts: 4,297
Default

nAo is offline   Reply With Quote
Old 01-Jun-2005, 21:19   #6
j^aws
Senior Member
 
Join Date: Jun 2004
Posts: 1,908
Default

Quote:
Originally Posted by nAo
Henry Moreton has filed with NVidia a lot of patents regarding various hw tesselators architectures, I believe there are even more recent patents from him on UPSTO database.
Yep, he sure has plenty of tesselation type patents...

HENRY MORETON

Interestingly, this particular patent has Mori et al from a Toshiba GPU patent cited as a reference. Remember this patent?

http://www.beyond3d.com/forum/viewtopic.php?t=15986

Shhhh....it mentions the *R* word! :P
j^aws is offline   Reply With Quote
Old 01-Jun-2005, 22:43   #7
Farid
Artist formely known as Vysez
 
Join Date: Mar 2004
Location: Paris, France
Posts: 3,899
Default

Quote:
Originally Posted by version
http://web.axelero.hu/varga1973/rsx.JPG
SPEs? High Order Surface engines?

Keep off crack, dude.
__________________
- Power corrupts and absolute power is kinda neat.
- If at first you don't succeed, put it out for beta test.
--Internets
Farid is offline   Reply With Quote
Old 02-Jun-2005, 01:57   #8
Mythos
Member
 
Join Date: May 2004
Posts: 356
Default

Quote:
Originally Posted by Jaws
Quote:
Originally Posted by nAo
Henry Moreton has filed with NVidia a lot of patents regarding various hw tesselators architectures, I believe there are even more recent patents from him on UPSTO database.
Yep, he sure has plenty of tesselation type patents...

HENRY MORETON

Interestingly, this particular patent has Mori et al from a Toshiba GPU patent cited as a reference. Remember this patent?

http://www.beyond3d.com/forum/viewtopic.php?t=15986

Shhhh....it mentions the *R* word! :P
Jaws,
I was thinking about this whole GPU issue with Sony, Toshiba, and Nvidia. About whether someone got shafted out of the GPU deal or if the GPU was a last minute add in. However, I think it is probable that instead of wasted time spent that whatever work was done initially could be transfered over to the RSX (specially the good parts of the Toshiba GPU/Compatible with RSX). I can see that Sony had a goal it wanted to meet with the GPU and the Nvidia deal satisified those goals. (Add to it the patents each company advanced without any useage would be a waste.)
Mythos is offline   Reply With Quote
Old 02-Jun-2005, 04:38   #9
The GameMaster
Member
 
Join Date: Feb 2005
Posts: 109
Default

WGF 2.0 compliance patents it seems for future technologies that they will need to incorporate for their future products (NV6x+ GPU series) so they will be WGF 2.0 compliant for the upcoming Windows platform. Basically part of WGF 2.0 compliance is the GPU needs to be able to CREATE geometry. Certain technologies was built into the CPUs in the XBox360 to make the machine WGF 2.0 compliant even though the GPU is not. The Cell CPU, while it is able to create geometry... it is not able to do it in the method as described in WGF 2.0 compliance or the method's required for the extensive use as employed with the procedural synthesis. The ability to create geometry must be implemented in HARDWARE... not software for WGF 2.0 compliance.

Long story short this is for future nVidia products (NV6x+) not the NV50 series or the RSX which is suppost to be based on that technology. Can't say the R520 from ATI will be WGF 2.0 compliant either... same boat as nVidia, though with the inside track as they are cooperating with Microsoft may give them an inside line on WGF 2.0... regardless I don't expect that until the R6xx series GPUs from ATI.

The GameMaster...
The GameMaster is offline   Reply With Quote
Old 02-Jun-2005, 07:00   #10
Carl B
Friends call me xbd
 
Join Date: Feb 2005
Posts: 6,293
Default

There's absolutely no way the R520 will be compliant - the WGF2.0 standard hasn't even been finalized yet. Add to that that it's already been claimed to be a DX9.0c/1.0++ part and well there ya go. It would be stupid for the graphics makers to release a WGF2.0 compliant part this year, even if they were ready to do so, as it would deprive them of a possible forced upgrade cycle next year or in 2007 when Longhorn will bring the standard into being.
__________________
Somebody set up us the bomb.
Carl B is offline   Reply With Quote
Old 02-Jun-2005, 10:22   #11
one
Unruly Member
 
Join Date: Jul 2004
Location: Minato-ku, Tokyo
Posts: 4,705
Default

Quote:
Originally Posted by Jaws
Interestingly, this particular patent has Mori et al from a Toshiba GPU patent cited as a reference. Remember this patent?

http://www.beyond3d.com/forum/viewtopic.php?t=15986

Shhhh....it mentions the *R* word! :P
Wow, so this was really an RS patent? Now, in what way does the new nVIDIA patent develop on the Toshiba RS?
one is offline   Reply With Quote
Old 02-Jun-2005, 10:26   #12
london-boy
Me me me
 
Join Date: Apr 2002
Posts: 15,348
Default

So... errm... in layman's terms, what exactly will this allow?
london-boy is offline   Reply With Quote
Old 02-Jun-2005, 10:35   #13
nAo
Nutella Nutellae
 
Join Date: Feb 2002
Location: San Francisco
Posts: 4,297
Default

They are just citing some patents that share something in commong with their application. Toshiba patent was about a hw REYES implementation, but it was also about a programmable tessellator. I wouldn't look for connections that are not really there.
Moreton work it's not about REYES at all, it's about a number of fixed function processors designed around a number of basic processing steps involved in surfaces tesselation.
It might be someway similar to r500 hw tesselator, which is a fixed function hw block AFAIK, but it takes as input a number of parameters that can be generated by a special geometry shader.
nAo is offline   Reply With Quote
Old 02-Jun-2005, 20:40   #14
j^aws
Senior Member
 
Join Date: Jun 2004
Posts: 1,908
Default

Quote:
Originally Posted by Mythos
...
Jaws,
I was thinking about this whole GPU issue with Sony, Toshiba, and Nvidia. About whether someone got shafted out of the GPU deal or if the GPU was a last minute add in. However, I think it is probable that instead of wasted time spent that whatever work was done initially could be transfered over to the RSX (specially the good parts of the Toshiba GPU/Compatible with RSX). I can see that Sony had a goal it wanted to meet with the GPU and the Nvidia deal satisified those goals. (Add to it the patents each company advanced without any useage would be a waste.)
I don't look at this as someone who got shafted. But like you say, they had a goal. It's simple really, as any project would have three key elements, cost, delivery date and specification. As long as these criteria are met, it doesn't really matter on the actual means. In fact, it takes more courage to *switch* the status quo than mindlessly follow a particular path because of past precedents and inertia!

Quote:
Originally Posted by The GameMaster
...
Long story short this is for future nVidia products (NV6x+) not the NV50 series or the RSX which is suppost to be based on that technology. Can't say the R520 from ATI will be WGF 2.0 compliant either... same boat as nVidia, though with the inside track as they are cooperating with Microsoft may give them an inside line on WGF 2.0... regardless I don't expect that until the R6xx series GPUs from ATI.
Sony, nVidia and RSX don't need any WGF 2.0 spec to be agreed. They can *add* what they like to the PS3...
j^aws is offline   Reply With Quote
Old 02-Jun-2005, 23:35   #15
psurge
Member
 
Join Date: Feb 2002
Location: LA, California
Posts: 825
Default

nAo - do you understand exactly what the fixed function blocks in the patent are? It's kind of confusing to me, because AFAICT, they issue instructions to the vector engine to do actual work (and by throttling their instruction or I guess thread issue rate, load balancing is achieved). So... are they in charge of actually creating/destroying vertices, or...?
psurge is offline   Reply With Quote
Old 03-Jun-2005, 01:47   #16
version
 
Join Date: Jul 2004
Posts: 452
Send a message via ICQ to version
Default

http://www.cs.utexas.edu/users/billm...dering2010.pdf
__________________
Version of Majic12
version is offline   Reply With Quote
Old 03-Jun-2005, 10:03   #17
nAo
Nutella Nutellae
 
Join Date: Feb 2002
Location: San Francisco
Posts: 4,297
Default

Quote:
Originally Posted by psurge
nAo - do you understand exactly what the fixed function blocks in the patent are? It's kind of confusing to me, because AFAICT, they issue instructions to the vector engine to do actual work (and by throttling their instruction or I guess thread issue rate, load balancing is achieved). So... are they in charge of actually creating/destroying vertices, or...?
This patent describes a couple of configurations: the first one is pretty generic, the second one goes in deeper details and tell us fixed function engines perform a lot of different tasks, each task is a 'micro' step needed to tesselate or assemble primitives.
Each FFE is associated to at least one user-programmable step, it runs shaders (sending commands to the vertex processor), and it assembles/creates primitives generating new vertex indices (new vertices coordinates are store in vertex ram).
All the math work is accomplished by the vertex processor and the scheduler decides wich FFE has to serve.
In the last embodiment there are 4 FFEs, each FFE is associated with a specific task/program: a single-vertex program, a subdivision program, a mesh program and a general program.
For example the subdivision program is splitted in several task, each task runs a subprogram, the associated FFE performs fixed function tasks between each subprogram:
Quote:
The subdivision program suite includes six programs (or subroutines) that are used to subdivide one or more primitives. The six programs are an edge test program, a limit point program, a face control point program, an edge control point program, a vertex control point refinement program and edge data refinement program.
nAo is offline   Reply With Quote
Old 04-Jun-2005, 12:56   #18
j^aws
Senior Member
 
Join Date: Jun 2004
Posts: 1,908
Default

Maybe a vec4 + SFU cluster could act as a geometry/ vertex shader? 8)
j^aws is offline   Reply With Quote

Reply

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off

Forum Jump

Similar Threads
Thread Thread Starter Forum Replies Last Post
NVIDIA Showcases Graphics Technology At E3 Dave Baumann Press Releases 0 18-May-2005 14:56
CONFIRMED: PS3 to use "Nvidia-based Graphics processor& passerby Console Technology 700 15-Dec-2004 23:29
NVIDIA And Epic Games Showcase Unreal Engine 3 At E3 Dave Baumann Press Releases 0 11-May-2004 20:08
A year of nVidia Quitch 3D & Semiconductor Industry 39 12-Nov-2003 10:47
NVIDIA Delivers Quadro FX GO700 Dave Baumann Press Releases 0 25-Jun-2003 09:28


All times are GMT +1. The time now is 04:53.


Powered by vBulletin® Version 3.8.6
Copyright ©2000 - 2013, Jelsoft Enterprises Ltd.