[Roger Kohli]

I think we have had this discussion before, but isn't this very similar to PowerVR's TBDR?

ftp://download.intel.com/design/chip...s/30262503.pdf

Summary
5.1 What Is Zone Rendering Technology 3?

Zone Rendering Technology 3 is a process in which the screen is divided into several zones. Each
zone is completely cached and rendered on chip before being written to the frame buffer.

5.2 What Are the Benefits of Zone Rendering
Technology 3?

Zone Rendering Technology 3 has several benefits:
• Reduction in Depth and Color Bandwidth associated with conventional rendering
• Increased memory efficiency via better localization of data
• Increased on-chip processing speed due to decreased wait time for data
• Reduced power as a result of decreased memory bandwidth
• Increased effective pixel fill rates
• Increased headroom for larger resolution and color depth

5.3 Conclusions

The Zone Rendering Technology 3 architecture featured in the next-generation Intel GMCH, the
915G/915GV/910GL Express chipset with Intel GMA 900 graphics, provides improved
performance above conventional 3D architectures through efficient memory bandwidth usage and
optimal utilization of the render cache. The Intel GMA 900 graphics drivers provide software
support for this new architecture for both Direct3D and OpenGL, allowing both existing and
future 3D applications using these APIs to use Zone Rendering Technology 3 without the need
for modification.

[Dave Baumann]

Yes and no.

One thing that I've never seen them reference is whether they do any geometry culling - I think they render everything to the tile, but only save on the bandwidth.

[Xmas]

Originally Posted by DaveBaumann

Yes and no.

One thing that I've never seen them reference is whether they do any geometry culling - I think they render everything to the tile, but only save on the bandwidth.

Well, they claim "Increased effective pixel fill rates", so they must be doing at least some HSR. Maybe they're doing a Z-first pass.

[Ailuros]

I know it's OT but I got this one while snooping around in Intel's 2700G (MBX) whitepapers; just in relation to Dave's comment:

Small Object Culling
On a screen, the smallest visible element is a pixel. If a triangle fails to intersect with a pixel, it
will not be drawn on the screen. Many triangles like this can occur in an image due to complex
models that may be scaled, rotated, and transformed. The tile accelerator removes these unused
triangles, reducing the number of triangles to be processed by the 3D core.

ftp://download.intel.com/design/pca/...s/30094801.pdf

[Chalnoth]

Why are they attaching the number "3" to it, though?

[Kaotik]

Originally Posted by Chalnoth

Why are they attaching the number "3" to it, though?

Intel Extreme Graphics -> "1"
Intel Extreme Graphics 2 -> "2"
Intel Graphics(?) Media Accelerator 900 -> "3"
no?

[AzBat]

Check this page for Zone Rendering Technology 2...

http://www.intel.com/design/chipsets...ots/253525.htm

It has a PDF document about the technology that was included in the 865G chipset.

Tommy McClain

[Kaotik]

Originally Posted by AzBat

Check this page for Zone Rendering Technology 2...

http://www.intel.com/design/chipsets...ots/253525.htm

It has a PDF document about the technology that was included in the 865G chipset.

Tommy McClain

That pretty much confirms what I thought above.

[Dave Baumann]

http://www.beyond3d.com/reviews/inte...p?p=3#graphics

[Killer-Kris]

Just makes you wonder what a deferred renderer with 16 pipelines, shaders, and occluded pixel culling would perform like.