Beyond3D Forum

zchieply · 25-Jul-2012, 01:55

I was thinking about a architecture idea were one instruction is issued to multiple register files in a core. it would be implemented like this were you would heave the op code with two sets of three operands. you could also use vector instructions to run alot of data on two or four threads in a core. you would only need to fetch and decode on long instruction saving a lot of bandwidth and energy.

denev2004 · 25-Jul-2012, 04:31

Wouldn't that be the way how SnB AVX is organized?

Exophase · 25-Jul-2012, 05:12

Sounds more like VLIW with separate register "sides".. TI's TMS320C6x series DSPs does this.. Although both sides can access the other's register file, with restrictions.

VLIW is in between SIMD and standard superscalar. Of course the instruction sequencing is explicit and therefore don't refer to separate threads. Adding any kind of register file separation really makes it harder to extract the ILP you want, that traditional SIMD can't get at..

25-Jul-2012, 01:55	#1
zchieply Registered Join Date: Dec 2011 Posts: 6	SMID with SMT idea I was thinking about a architecture idea were one instruction is issued to multiple register files in a core. it would be implemented like this were you would heave the op code with two sets of three operands. you could also use vector instructions to run alot of data on two or four threads in a core. you would only need to fetch and decode on long instruction saving a lot of bandwidth and energy.

25-Jul-2012, 04:31	#2
denev2004 Member Join Date: Apr 2010 Location: China Posts: 143	Wouldn't that be the way how SnB AVX is organized? __________________ Well I'm not a native English speaker so there might be misuse through my words. I just hope it won't cause too much misunderstanding.

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25-Jul-2012, 05:12	#3
Exophase Senior Member Join Date: Mar 2010 Location: Cleveland, OH Posts: 1,581	Sounds more like VLIW with separate register "sides".. TI's TMS320C6x series DSPs does this.. Although both sides can access the other's register file, with restrictions. VLIW is in between SIMD and standard superscalar. Of course the instruction sequencing is explicit and therefore don't refer to separate threads. Adding any kind of register file separation really makes it harder to extract the ILP you want, that traditional SIMD can't get at..

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