[jonabbey]

I'm still happily using my US launch 60GB, but I've been eyeing a new PS3 for the power savings.

[BoardBonobo]

Like the have mentioned there are a number of Good videos available. Just make sure you've got all the bits you need. Small and medium Philips screwdrivers, thermal paste ( i use arctic silver myself), some thermal paste remover and some purified water to clean the heatsink and spreaders with. I also use a kitchen sponge cut up into quarters for cleaning the old paste of with. I tend to keep a little stick magnet with me as well. You can attach it to the side of a screw driver to help remove hard to reach screws.

Always make sure you are static free as well.

[The Seventh Taylor]

Well, the discussion about the new, slimmer PS3 may continue in this thread

http://forum.beyond3d.com/showthread.php?p=1656070

but until GamesCon 2012 (or more likely shortly after release when a company like iFixit publishes a teardown report) I'll be left wondering what the new motherboard looks like -- particularly whether Cell and RSX have been shrunk and/or integrated.

[The Seventh Taylor]

Back now to the original question of semiconductor integration for PS3...

Chipworks just published this analysis of how the PS Vita uses a Chip-on-Chip SiP.

http://www.chipworks.ca/en/technical...3d-but-not-3d/

Would the next PS3 likely use a similar solution? Has anything been published about this yet?

[Grall]

Stacking two high-wattage ASICs on top of each other would be fatal, from a heat-management perspective. Especially with additional interposers as used in the vita.

[onQ]

Originally Posted by Grall

Stacking two high-wattage ASICs on top of each other would be fatal, from a heat-management perspective. Especially with additional interposers as used in the vita.

Cell & RSX side by side in a SOC with the Memory stacked on top ?

[Prophecy2k]

Originally Posted by Grall

Stacking two high-wattage ASICs on top of each other would be fatal, from a heat-management perspective. Especially with additional interposers as used in the vita.

Surely it would depend on how high wattage they are right? Pehaps not for 3D stacking of the two ASICs ontop of each other, but side by side like that good chap above me said?

If they got down to 28nm for CELL and RSX what would the power consumption be like?

[babybumb]

http://www.linkedin.com/pub/elizabet...ard/45/718/7b7

Saw this on DF. Sony skipping 28nm straight to 22nm?

PlayStation 3
Team Members: Elizabeth Gerhard
- Owned the array design for a 1.6GHz TLB array in the 90nm node.
- Co-owned the delivery of a 128K custom L2 Cache array in the 90nm node.
- Led a team that delivered the L2cache array macro in the 65nm and 45nm nodes.
- Owned the register file cell qualification analysis in the 22nm node
- Owned the design of a 3.2GHz one read one write custom register file array in the 22nm node.