[Grall]

It's what remains of Intel's latest (last?) attempt at discrete graphics. A bit saddening and disheartening, but you can't argue with 1Tflop of computing performance. I assume that's 1Tflop of double precision (or maybe better - x86 FPU is like 80 bits innit) maths. Should also be easier to program for than a GPU, which might make up for some of the brute-force top performance difference compared to today's top of the line graphics cards.

Has anyone seen any nudiehotss with the shround and heatsink off yet, or even some hardcore nekkid core without heatspreader cap of this thing yet?

Also - hardware specs? Clock speeds, cache amounts, power draw figures... The whole kit and kaboodle! The offiical PDF that Intel links to doesn't say anything about that.

[rpg.314]

It doesn't look like Intel is making a play for discrete GPU at all with this. I am not surprised considering how LRB turned out.

[Exophase]

Originally Posted by Grall

(or maybe better - x86 FPU is like 80 bits innit)

Its SIMD certainly isn't, and I would hardly expect such a thing to surface with MIC's.

[Grall]

Originally Posted by rpg.314

It doesn't look like Intel is making a play for discrete GPU at all with this.

No, of course not... It has no video connectors after all.

Originally Posted by Exophase

Its SIMD certainly isn't

*Ahem* x87 FPU I should probably have said. The old stack-based hellish creation. My bad.

[Exophase]

Originally Posted by Grall

*Ahem* x87 FPU I should probably have said. The old stack-based hellish creation. My bad.

Yeah, I know what you meant, just saying that there's no reason that would show up on MIC's main compute capabilities (its SIMD). However (and much to my surprise), it would appear that the instruction set does retain support for x87 and even SSE.. it's not totally clear since the ISA manual doesn't list legacy instructions but there's some information about saving and restoring x87 and XMM state.

[3dilettante]

It's still using the old P54 core as its basis, so x87 will remain. The decision to move the vector ISA closer to AVX may mean full deprecation would take about as long it would for the mainline ISA (if/when that happens), if the two remain separate for more than 2-3 generations.

[Ninjaprime]

Originally Posted by Grall

It's what remains of Intel's latest (last?) attempt at discrete graphics. A bit saddening and disheartening, but you can't argue with 1Tflop of computing performance. I assume that's 1Tflop of double precision (or maybe better - x86 FPU is like 80 bits innit) maths. Should also be easier to program for than a GPU, which might make up for some of the brute-force top performance difference compared to today's top of the line graphics cards.

Has anyone seen any nudiehotss with the shround and heatsink off yet, or even some hardcore nekkid core without heatspreader cap of this thing yet?

Also - hardware specs? Clock speeds, cache amounts, power draw figures... The whole kit and kaboodle! The offiical PDF that Intel links to doesn't say anything about that.

On the power useage, they are saying ~300 watts here and there, so I'm guessing its got a smart power system that lets it push right up to the PCI-E limit, so I'd call it 300 watt tdp. IIRC, they quoted power figures a while ago on the knights corner docs that said 1.6 ghz target clock speed, inital versions being 1.2ghz. I believe it referenced the 1.2ghz version when refering to the 1Tflops in DGEMM, so theoretically theres 33% room for improvement there.

[pcchen]

Apparently Intel made a MIC based cluster, it has 9800 cores, Rpeak @ 180.99 TFLOPS, Rmax @ 118.60 TFLOPS, and 100.8 kW power consumption for the entire system. This makes the system a little more than 1GFLOPS per watt, which is comparable to other GPGPU based supercomputers, but less than BlueGene/Q systems (which achieve > 2GFLOPS per watt for many large systems).

[DavidC]

There's an article that says the Xeon Phi can do 4-5GFlops/watt. That makes a 1TFlop version 200-250W. As for cores, the total is 64 but some are likely disabled for redundancy purposes. The rumors are 54-62.

[Rodéric]

Are they streamlined x86 cores and if so, how different are they ?

[3dilettante]

They are modified P54C cores. (edit: This may not be the case for the latest chip, but I don't know now.)
They aren't streamlined so much as they are based on a design from before x86 grew up.

[swaaye]

It sounds like Larrabee and P5 have some similar design concepts but that's about it. It's also not really Atom-like.
http://www.anandtech.com/show/2580/3

[Exophase]

Originally Posted by 3dilettante

It's still using the old P54 core as its basis, so x87 will remain. The decision to move the vector ISA closer to AVX may mean full deprecation would take about as long it would for the mainline ISA (if/when that happens), if the two remain separate for more than 2-3 generations.

I don't think using P54 as a basis is any real reason to expect x87 to remain, when they added all sorts of other extensions (not least of all x86-64), must have a pretty different cache architecture that can support scatter/gather efficiently and has integrated L2, throws out the original functionality of the "V" pipe altogether for all the vector stuff.. adds SMT.. surely needs a longer pipeline to hit multiple GHz.. you know I'd be really interested in seeing how much Pentium influence can even still be seen..

IMO Intel should really embrace opportunities to throw x87 out where it does no real harm. But they're probably holding on to illusions of people running legacy binaries on this..

[3dilettante]

Originally Posted by Exophase

I don't think using P54 as a basis is any real reason to expect x87 to remain,

Some additional commentary makes me wonder now if the P54C is the basis of the 22nm cores, but I have no additional data to confirm.
However, as far as the initial architecture went, the decision to use P54 was to minimize the amount of design and validation work done not related to getting the vector extensions running.

when they added all sorts of other extensions (not least of all x86-64), have a pretty different cache architecture that can support scatter/gather efficiently,

The former would involve some reworking of some of the internals of the scalar side, x86-64 was designed to allow an evolutionary change to the front end.
What parts of the 64-byte cache line for every vector load operation makes you think the memory pipeline supports scatter/gather very well? The internals of the core should handle most of the changes without the cache knowing.

throws out the original functionality of the "V" pipe altogether for all the vector stuff.. adds SMT.. surely needs a longer pipeline to hit multiple GHz.. you know I'd be really interested in seeing how much Pentium influence can even still be seen..

Depends on the rumors on whether they used the orginal P54 RTL as a basis for the original Larrabee have some truth to them.

IMO Intel should really embrace opportunities to throw x87 out where it does no real harm. But they're probably holding on to illusions of people running legacy binaries on this..

ISA compatibility, and the possibility of future integration into the main line. If the latter is true, Larrabee's successors would no sooner drop x87 than the mainline chips.

[mczak]

Originally Posted by Exophase

Yeah, I know what you meant, just saying that there's no reason that would show up on MIC's main compute capabilities (its SIMD). However (and much to my surprise), it would appear that the instruction set does retain support for x87 and even SSE.. it's not totally clear since the ISA manual doesn't list legacy instructions but there's some information about saving and restoring x87 and XMM state.

There's no SSE support. The ISA docs explicitly mention no instructions using xmm or mmx regs are supported. Intel also kicked out a bunch of other useful instructions (well ok at least one, cmov, though it has always been a AMD and not a intel favorite...), while keeping some old garbage noone (including compilers) ever uses.
An odd choice imho I'd have thought some cheaply implemented SSE unit (if you really want some "compatible" FPU on the "main" cpu) would have been a better choice than the x87 crap (and probably not really more expensive even as you wouldn't need to deal with extended precision).

[rpg.314]

Originally Posted by Exophase

Yeah, I know what you meant, just saying that there's no reason that would show up on MIC's main compute capabilities (its SIMD). However (and much to my surprise), it would appear that the instruction set does retain support for x87 and even SSE.. it's not totally clear since the ISA manual doesn't list legacy instructions but there's some information about saving and restoring x87 and XMM state.

It's not compatible with any other x86 processor, so they must have removed something.

[rpg.314]

Originally Posted by Exophase

I don't think using P54 as a basis is any real reason to expect x87 to remain, when they added all sorts of other extensions (not least of all x86-64), must have a pretty different cache architecture that can support scatter/gather efficiently and has integrated L2, throws out the original functionality of the "V" pipe altogether for all the vector stuff.. adds SMT.. surely needs a longer pipeline to hit multiple GHz.. you know I'd be really interested in seeing how much Pentium influence can even still be seen..

I think they are targeting ~1GHz.

IMO Intel should really embrace opportunities to throw x87 out where it does no real harm. But they're probably holding on to illusions of people running legacy binaries on this..

That's the entire usp of the thing.

[Exophase]

Originally Posted by rpg.314

I think they are targeting ~1GHz.

They have released at 32nm targeting 1GHz, but AFAIK the original projections were much higher. I've heard as high as 2GHz.

Originally Posted by rpg.314

That's the entire usp of the thing.

What does usp stand for..?

I thought the point was that being x86 made it easy to migrate tools to it and was just a useful paradigm for scalar control code. I've seen Intel brag about how quickly some have ported large HPC projects to MIC, but I haven't heard them claim anyone was reusing legacy binary code on it. Especially old x87 code.

[rpg.314]

Originally Posted by Exophase

They have released at 32nm targeting 1GHz, but AFAIK the original projections were much higher. I've heard as high as 2GHz.

AFAIK, the gpu version (on 45 nm) was supposed to hit 1GHz. The 22nm will run at 1GHz.

I thought the point was that being x86 made it easy to migrate tools to it and was just a useful paradigm for scalar control code. I've seen Intel brag about how quickly some have ported large HPC projects to MIC, but I haven't heard them claim anyone was reusing legacy binary code on it. Especially old x87 code.

Well, they aren't going to remove x87 even if no body is using it.

[DavidC]

Originally Posted by rpg.314

AFAIK, the gpu version (on 45 nm) was supposed to hit 1GHz. The 22nm will run at 1GHz.

Well, the 45nm Knights Ferry dev boards were running at 1.2GHz. Maybe you mean 2GHz? :P

[Simon F]

Originally Posted by Exophase

What does usp stand for..?.

Unique Selling Point.

[rpg.314]

Originally Posted by DavidC

Well, the 45nm Knights Ferry dev boards were running at 1.2GHz. Maybe you mean 2GHz? :P

Yeah.

[hkultala]

Originally Posted by 3dilettante

It's still using the old P54 core as its basis, so x87 will remain. The decision to move the vector ISA closer to AVX may mean full deprecation would take about as long it would for the mainline ISA (if/when that happens), if the two remain separate for more than 2-3 generations.

Knights corner has NOTHING to do with P54/original pentium.

Intel SCC was based on Pentium, but MIC/larrabee/knights corner/knights ferry is completely different thing.

Some people confused SCC with MIC and started posting that MIC/larrabee/knights is based pentium, and then this misinformation started circulating, but
1) Intel has never said that MIC is based on pentium
2) They have quite different architecture. For example:
A) MIC/larrabee/knights line has single scalar pipeline, pentium has two.
B) MIC has HypeThreading.
C) MIC has x86-64.

It's much closer to Atom than Pentium, but it's not Atom either.

[3dilettante]

Originally Posted by hkultala

Knights corner has NOTHING to do with P54/original pentium.

Intel SCC was based on Pentium, but MIC/larrabee/knights corner/knights ferry is completely different thing.

Some people confused SCC with MIC and started posting that MIC/larrabee/knights is based pentium, and then this misinformation started circulating, but

Some of those people were Intel stating Larrabee was derived from the original Pentium.
That was probably the starting point of that particular factoid.