[kyetech]

Its not clear if this is going to be a 14nm capable fab (at some point) which starts out on another process first, or if this going to be 14nm off the bat in 2013.

But Intel is targeting 22nm by end of 2011. So 14nm seems aggressive for 2013?

What are your thoughts?

http://www.pcmag.com/article2/0,2817,2380625,00.asp
http://newsroom.intel.com/community/...and-innovation

If they pull this off then its going to lead to some monster chips in 2014. I believe things must level off after that surely? I mean every other company just seems to be struggling so much to get new processes out the door.

[AlphaWolf]

It's not completely out of line with previous roadmaps (although I had seen 16nm, not 14).

[rpg.314]

Should be 16nm, otherwise intel are also going off the itrs roadmap.

[Erinyes]

The 14 nm node was confirmed In the Intel Investor meeting the other day, launching two years after 22nm as expected.

But was the node changed sometime this year/last year? AFAIK the next node after 22nm was supposed to be 16nm. Did they have a sudden change in plans? Even TSMC's next node after 20nm(i suppose they arent doing a 22nm node?) is going to be 14nm afaik.

Now comparing size,

(16*16)/(22*22) = 53%

(14*14)/(22*22) = 40%

The first figure of 53% is in line with all the process node advances in the recent past with density roughly doubling every node. The second figure of 40% is a departure from that pattern.

[Arun]

They renamed 16nm to 14nm. The design rules were finalised before they decided to rename it AFAIK. This is very different from TSMC's 40G process which *does* have higher density than 45LP (which is a real process used in most of Qualcomm's chips and at least one from NXP's TV SoC group now part of Trident).

However, given that Intel 32nm's density is as good as TSMC's 28nm one, it's a very defensible position. Why make your process lead appear smaller than it really is? On the other hand, TSMC's 14nm process is very likely to use e-beam or EUV, whereas Intel's will still be dual immersion. So if that's the case, TSMC really might have a density advantage and it'd have been fairer to keep calling it 16nm. Not that being fair has anything to do with this kind of marketing, mind you.

[Humus]

So the specified number of nanometers is not really the physical number of nanometers but some kind of marketing number?

Sounds a bit like this:
http://dilbert.com/strips/comic/2011-05-10?Page=3

[3dcgi]

http://spectrum.ieee.org/semiconduct...-possibilities

Let’s start by defining our terms. Today’s most advanced microprocessors use a 32-nanometer process, and thus are said to be at the 32-nm node. To get a sense of how infinitesimal 32 nm is, consider that to span the width of the lowercase letter l on this page, you would need to bunch together more than 9500 32-nm objects. Node in this context has historically been used to refer to the size of the smallest parts of the transistors on the chips. Until the late 1990s, that was typically a feature called a gate. But there is a very fuzzy relationship between the technology node’s number and the actual dimensions of the gate it purports to signify. In fact, the International Technology Roadmap for Semiconductors, the industry’s guide star, abandoned the term in 2005, but its usage has persisted.

The article goes on to discuss why memory process size differs from logic.

The half-pitch of the metal lines on the first and densest level is special, because that distance was what once defined not only the half-pitch but also the gate and, consequently, the node. But by 2000, it was a dicey relationship. The half-pitch was becoming bigger than the node.

So, for example, in 2005 the gate width on an Intel micro-processor was 32 nm. The node was called ”65 nm,” but the half-pitch for the first level of wires was 105 nm. Confused yet?

The half-pitch of the first wiring layer is the defining feature for memory chips, while the gate length is the gauge for logic manufacturers. Neither is entirely representative of the node.

[Erinyes]

Originally Posted by Arun

They renamed 16nm to 14nm. The design rules were finalised before they decided to rename it AFAIK. This is very different from TSMC's 40G process which *does* have higher density than 45LP (which is a real process used in most of Qualcomm's chips and at least one from NXP's TV SoC group now part of Trident).

However, given that Intel 32nm's density is as good as TSMC's 28nm one, it's a very defensible position. Why make your process lead appear smaller than it really is? On the other hand, TSMC's 14nm process is very likely to use e-beam or EUV, whereas Intel's will still be dual immersion. So if that's the case, TSMC really might have a density advantage and it'd have been fairer to keep calling it 16nm. Not that being fair has anything to do with this kind of marketing, mind you.

Wow I had no idea 45LP was ever used Why didnt Qualcomm just go with 40G?

Rename? I would have understood if it was GF but for Intel its highly unusual is it not?

And its not like they're a fab where they need to be doing marketing (And even if they were a fab im sure the people designing chips wouldnt be dumb enough to fall for such marketing)

Btw this is OT but what is GF's next process node? 22nm or are they going straight to 20nm?

[Arun]

Originally Posted by Erinyes

Wow I had no idea 45LP was ever used Why didnt Qualcomm just go with 40G?

I assume you meant 40LP. They were supposed to start with 45LP and shrink to 40LP later, but they didn't and even their LTE chip is 45nm. One possible exception is the latest-generation dual-core MSM8x20 which uses triple gate oxide, and I doubt that's even available on 45nm. But who knows...

Rename? I would have understood if it was GF but for Intel its highly unusual is it not?

And its not like they're a fab where they need to be doing marketing (And even if they were a fab im sure the people designing chips wouldnt be dumb enough to fall for such marketing)

My guess: Atom. It's very important for them to highlight just how significant the process gap is there both for public marketing and to convince OEMs they can be competitive.

Btw this is OT but what is GF's next process node? 22nm or are they going straight to 20nm?

IIRC (could be wrong), it's 22nm SOI for AMD and 20nm Bulk for everyone else (ala 32/28nm today). Unfortunately, it's still not Fully Depleted SOI.

[Erinyes]

Originally Posted by Arun

I assume you meant 40LP. They were supposed to start with 45LP and shrink to 40LP later, but they didn't and even their LTE chip is 45nm. One possible exception is the latest-generation dual-core MSM8x20 which uses triple gate oxide, and I doubt that's even available on 45nm. But who knows...

I dont know too much abt the semiconductor industry in general, just what i read on the internet. But i thought Tegra 2 was on 40G or am i mistaken? Thats why i suggested 40G for Qualcomm

And from what i understood you're saying MSM 8X60 is on 40LPG?

My guess: Atom. It's very important for them to highlight just how significant the process gap is there both for public marketing and to convince OEMs they can be competitive.

That might well be the case, after all they accelerated the 14nm Atom to at least a year ahead of the schedule they've been following for Atom so far. ARM will be on 20nm by that time(and Project Denver also will be out by then?) but Intel will be ahead by like two years at that point

IIRC (could be wrong), it's 22nm SOI for AMD and 20nm Bulk for everyone else (ala 32/28nm today). Unfortunately, it's still not Fully Depleted SOI.

Thats what i remember reading as well, but havent read any updates on GF's plans for quite a while now so was just wondering.

[Arun]

Originally Posted by Erinyes

I dont know too much abt the semiconductor industry in general, just what i read on the internet. But i thought Tegra 2 was on 40G or am i mistaken? Thats why i suggested 40G for Qualcomm

And from what i understood you're saying MSM 8X60 is on 40LPG?

Tegra 2 and Kal-El are both on 40LPG, MSM8x60 is either on 40LPG or on an unannounced 45LPG process (which wouldn't make much sense). Interestingly, triple gate oxide is going away on 28nm in favour of greater gate Vt variations which are cheaper to implement, especially on a High-K process. This is the case for both TSMC 28HPM and GF 28HPP.

[dkanter]

Originally Posted by Humus

So the specified number of nanometers is not really the physical number of nanometers but some kind of marketing number?

Sounds a bit like this:
http://dilbert.com/strips/comic/2011-05-10?Page=3

Humus - that's exactly correct. It used to be that a Xnm process was denser than an (x+k)nm process. However, that's no longer really totally true.

TSMC's 40nm is denser and faster than their 45nm process, but it may not be denser than IBM's 45nm process.

In one of my articles, I highlighted this trend:
http://www.realworldtech.com/page.cf...109003617&p=11

You can see in the first chart that Intel's 45nm process is literally faster than most other 28nm/32nm processes. OTOH, their SRAM density isn't quite as impressive as TSMC's, although this may be a function of the type of comparison being made as I discuss below.

Basically, density tends to scale reasonable well with the marketing name of the process, but not the speed.

David