Thread: 22 nm Larrabee
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Old 08-Apr-2013, 05:28   #1115
LiXiangyang
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Join Date: Mar 2013
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MiC's L1 cache is not programmable, the inter-thread commuications on MiC is pretty much like the case of CPU. Intel's developer's forum is near, I will definitely go there to verifty if my experience with MiC is merely an exception.

Last edited by LiXiangyang; 08-Apr-2013 at 05:40.
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