2 APUs, Phoenix and Phoenix2 are different chips. Also should RDNA "3.5" be counted as separate? That's coming to at least 3 APUs by the looks of it (Strix Point, smaller version of Strix Point and Strix Halo)
On look, Ham is useless once again when he doesn't have a car seconds faster than the rest :rolleyes:
(yes I realize it's irrelevant what the rest does since they've decided Verscrappen wins whatever the biggest sponsors want few years back)
The only differences that could really be are related to which units are disabled and which enabled and whatever possible latency penalties (probably nothing measurable in practice) it might result in if enabled/disabled units are stacked together vs spread out (which then could bring miniscule...
Intel has been using matrix accelerators ("AI" "tensor cores", in Intels case "XMX cores") since day 1
edit: or did you mean frame generation instead? That's something Intel hasn't released yet.