View Full Version : ClawHammer: Everything Goes As Scheduled
ClawHammer: Everything Goes As Scheduled
Posted 2/12/02 at 11:37 pm by Rat
As our sources in AMD have reported, the closest partners of the company have already received the first samples of the ClawHammer processor with A0 stepping for the uni-processor systems made with the 0.13-micron technology in Dresden. Thus, the introduction of x86-64 technology goes as scheduled: AMD was going to start ClawHammer sampling in the first half-year. The first ClawHammer release in the desktop variant is scheduled to the fourth quarter of this year, and there’s no reason to doubt the reality of these plans. Also, the first ClawHammer samples are reported to be showcased at CeBIT show, which is held in the middle of March in Hanover.
We shall remind, that AMD will introduce a number of improvements in Hammer directed both to support the 64-bit code, and to improve the performance. 8 additional SSE registers and 8 general-purpose registers will be added in Hammer. Simultaneously, all general-purpose registers will be extended to 64 bits. Also, AMD brings out support for SSE2 instructions system and improves prefetching algorithms. The processor will have an integer pipeline lengthened up to 12 stages and 17-stage FPU pipeline, with good scalability for further frequency increase. Also, the CPU will have a built-in one- or two-channel memory controller supporting PC2700 DDR SDRAM.
Among some other interesting things I would also like to mention the possibility to connect two processor cores to a single memory controller, which should theoretically allow placing two computing cores into a single processor package. If AMD uses this possibility, though it is most likely to be intended for server Sledgehammer processors, there will appear a powerful alternative to Intel’s Hyper-Threading.
Also AMD official confirmed that mass Hammer processors will be provided with an HIS metal lid improving the heat dissipation from the processor die and protecting it against mechanical damages.
Even more interesting details about ClawHammer I read over at the Ukrainian Composter site. According to the information they received from AMD in an unofficial conversation, ClawHammer will be about 30% faster than Athlon XP working at the same frequency. By the way, bearing in mind the fact that ClawHammer 3400+ should be released in the end of the year already, AMD should again surpass Intel in terms of performance of its latest desktop CPUs, since at that time Intel will offer only 3GHz Pentium 4 :smile:
http://www.xbitlabs.com/news/story.html?id=1013575024
So it will be around 30% faster than the Athlon XP at the same frequency :eek:
Yeah, 30% is what a few folks said. I think the 50% faster kicks in when you recompile for x86-64, the extra registers are likely where they get a decent boost.
These marketing numbers are getting out of hand. 3400+, is SUPPOSE to mean it's equivelent to a 3.4GHz TBird's performance extrapolated from a 1GHz TBird --probably running on SDR :wink:. In any case, I'm not entirely convinced it'll be ahead of the P4. Of course, that's because I don't think DDR in its current state can meet modern x86 MPU's bandwidth demands, I think Tom's overclocking articles definately made that VERY clear.
Johnny Rotten
15-Feb-2002, 21:20
If its not ahead of the P4, then they will have failed in my eyes and alot of others as well.
Fortunately this shouldnt be the case. The Athlon is [currently] performance equivalent to the P4, just losing out on future scalability. [Claw]Hammer should have plenty of future headroom as WELL as being faster clock for clock.
Yeah, 30% is what a few folks said. I think the 50% faster kicks in when you recompile for x86-64, the extra registers are likely where they get a decent boost.
I agree. Maybe the best reason to use the i86-64 is the extra registers.
insomnia
16-Feb-2002, 08:51
i bet the coming 0.13µ xps will give a fair fight to p4s, not at clock speeds, but at computing power. And if intel is going according it plans and the last speed to come out this year is 2.8G and amd hammer is rated 3400+, until now the pr rating has been quite right, northwood tipped the balance a little, but not 2.8->3400 much. I just wish there will be graphics card to do hammer any justice, gf4ti 4600 mem bandwith should be doubled, and then we can start talking, and the price halved=)
Some Hammer chipsets news: http://www.siliconstrategies.com/story/OEG20020220S0070
AMD announces chip set and third-party support for 'Hammer' 64-bit processor line
Semiconductor Business News
(02/21/02 00:50 a.m. EST)
SUNNYVALE, Calif. -- Gearing up to enter the high-end microprocessor race, Advanced Micro Devices Inc. here today disclosed the first details of its chip set line designed for its upcoming family of 64-bit processors.
The company also announced that it is working with Acer Laboratories, Nvidia, Silicon Integrated Systems and Via Technologies to help co-develop third-party chip sets for its 64-bit processor line.
AMD's own chip set line--dubbed the AMD-8000 series--is designed to work with the company's code-named "Hammer" family of 64-bit processors. The Sunnyvale-based company is reportedly sampling the "Hammer" chips, with volume shipments due out in early-2003--or sooner, according to analysts.
"Hammer" is expected to compete against Intel Corp.'s 64-bit processor line, most notably McKinley. This chip is the follow-on product to Intel's existing 64-bit processor, dubbed Itanium.
AMD's chip set will make use of the HyperTransport I/O technology, which will increase the overall throughput in servers and other systems. "We believe the AMD-8000 series of chip sets will represent a major breakthrough in system chip set design," declared Ed Ellett, vice president of Marketing for AMD's Computation Products Group.
When formally introduced later this year, the AMD-8000 series of chip sets will consist of several components, including the AMD-8111 HyperTransport I/O hub, the AMD-8131 HyperTransport PCI-X tunnel, and the AMD-8151 HyperTransport AGP3.0 graphics tunnel.
The chip set will be available in the fourth quarter of 2002.
It will fail for several reasons:
1) Costs to produce such CPU must be high, and people do not appreciate paying premium price for AMD cpus.
2) Noone is going to compile programs to take advantage of its propritary 64bit instructions, look, even the intel 64 bit CPU is not doing well.
3) DDR memory is pathetic.
4) In order to upgrade to that CPU the poor XP owners will have to replace motherboard, cpu and probably RAM, that in case if AMD wakes up and starts using RDRAM. For intel owners it will be just the matter of replacing the chip.
5) Via.
On 2002-02-24 01:27, Dmitry wrote:
It will fail for several reasons:
Bah!
1) Costs to produce such CPU must be high, and people do not appreciate paying premium price for AMD cpus.
Die sizes at 0.13:
Thoroughbred: 80mm²
Clawhammer: 104mm²
Northwood: 145mm²
Which CPU will therefore be more costly to produce..?
2) Noone is going to compile programs to take advantage of its propritary 64bit instructions, look, even the intel 64 bit CPU is not doing well.
Even if no one compiles for AA64/x86-64 it will be the fastest IA32/x86-32 CPU. But OS support will be there, and where a OS is there are programs (remember the first 32bit OSs?).
3) DDR memory is pathetic.
Please elaborate.
4) In order to upgrade to that CPU the poor XP owners will have to replace motherboard, cpu and probably RAM, that in case if AMD wakes up and starts using RDRAM. For intel owners it will be just the matter of replacing the chip.
How many sockets have we seen lately from Intel? And how long does AMD uses (and will continue to do so with Thoroughbred and beyond) Socket-A? You also cried that you where not able to upgrade your P3 to a P4, right? :smile:
5) Via.
Please visit: http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_4699_4741,00.html
AMD won't depend so much on VIA this time, and others are also working on K8 chipsets.
Die size isn't necessarily equal to lower cost, yields are where it's at.
DDR isn't pathetic, but it isn't good either. Scaling the frequency and maintaining aggressive timings with DDR on motherboards is difficult. JEDEC is also not on the ball when it comes to formalizing specs, chances are Hammer might get delayed because certian DDR specs haven't been finalized or it might be the case they have to resort to dropping support for faster DDRRAM. In Tom's overclocking tests, it clearly shows DDR just isn't upto delivering the bandwidth needed by number crunching beasts such as a 3.0GHz P4.
The Clawhammer will NOT NECESSARILY be the fastest IA32/x86 MPU. The P4 with DRDRAM and a 533MHz bus is PLENTY of competition. It'll all depend on how high Intel decides to scale the P4.
Repeat after me, Clawhammer isn't the greatest thing since sliced bread. There are sooooooo many droids out there continually touting the great performance of a processor about which little is known.
Via, SiS and ALi make cheap buggy garbage. nVidia and AMD really are only ones on the current list of chipset designers that have the potential to make any real head way into the workstation/server market. It would be nice if they could get Serverworks, Compaq, IBM and other to build chipsets for them, AMD is in desperate need to get a good brand name backing them. The workstation/server market is VERY picky about reliability and quality, something that currently AMD processors fail to demonstarte to said group.
On 2002-02-24 06:29, Saem wrote:
Die size isn't necessarily equal to lower cost, yields are where it's at.
Yield also depend on die size. Murphy's law can also be applied on die size/yield, the bigger the chip the worse the yield. Take a look here: http://img.cmpnet.com/isd/editorial/1995/asiccolumn95091.gif (Very old graph from 1995, assumes 2 defects per mm²)
You can also download the "Gross and Net Die Calculator" from http://www.icknowledge.com/misc_technology/miscelaneous_technology.html and calculate the numbers for the different die sizes.
DDR isn't pathetic, but it isn't good either. Scaling the frequency and maintaining aggressive timings with DDR on motherboards is difficult.
It's indeed more difficult than with DRDAM, but nevertheless we will see DDR333, DDR400 and DDRII/533 becoming mainstream, question is when.
JEDEC is also not on the ball when it comes to formalizing specs, chances are Hammer might get delayed because certian DDR specs haven't been finalized or it might be the case they have to resort to dropping support for faster DDRRAM.
The Hammers will support PC2700/DDR333, which will be standardized in the following weeks, enough time before the Hammer launch - no need for a delay.
In Tom's overclocking tests, it clearly shows DDR just isn't upto delivering the bandwidth needed by number crunching beasts such as a 3.0GHz P4.
Single channel DDR isn't up to the task. Remember that it looks like DDR will be the main platform for the P4 in the future.
The Clawhammer will NOT NECESSARILY be the fastest IA32/x86 MPU. The P4 with DRDRAM and a 533MHz bus is PLENTY of competition. It'll all depend on how high Intel decides to scale the P4.
You mentioned THG's article above, which shows that even the Athlon/Thoroughbred will fare quite well against future P4, not to talk about a Clawhammer at a PR of 3400+.
Repeat after me, Clawhammer isn't the greatest thing since sliced bread. There are sooooooo many droids out there continually touting the great performance of a processor about which little is known.
Well, if AMD delivers what *is known* those "droids" will be right.
Via, SiS and ALi make cheap buggy garbage. nVidia and AMD really are only ones on the current list of chipset designers that have the potential to make any real head way into the workstation/server market. It would be nice if they could get Serverworks, Compaq, IBM and other to build chipsets for them, AMD is in desperate need to get a good brand name backing them. The workstation/server market is VERY picky about reliability and quality, something that currently AMD processors fail to demonstarte to said group.
Rumours has it that prototype Hammers already run on Alpha motherboards, I wouldn't be too concerned about the motherboard situation.
The Athlon only did well with a significant increase in the FSB, something that the Athlon will NOT be getting in it's 0.13 incarnation. Likely due to the fact AMD doesn't really care to release a new FSB only to can it for the Hammer shortly after.
Also, die size is a contributing factor but doesn't say anything about the cost of the waffer -I believe they're using SOI, it's quite expensive- or chip complexitity, number of metal layers and so on. The thing is, die size isn't necessarily telling of cost. I believe they need such a small die size to offset the potentially lower -with respect to their current line up- yield.
Dual channel DDR is not a good solution. nVidia has shown this, to have the board run stability -expected by picky consumers such as I and the workstation market- you can't aggressively clock it. It drops down to 100MHz instead of 133MHz. Also, even if you run it in the aggressive mode, I believe the timings goto 3, instead of 2.5. 4 layer PCBs and dual channel DDR don't mix. Dual channel DRDRAM, seems very capable of this, however. In the begining it was on 6 layers, however, they've gotten around it and many overclockers are easily uping the FSB and DRDRAM well above 533MHz. As for DDRII, I believe -can't remember- it has startling similarities to DRDRAM, isn't it supposed to be quite serialized rather than parallel and packetized?
Althornin
24-Feb-2002, 23:16
" 4 layer PCBs and dual channel DDR don't mix. Dual channel DRDRAM, seems very capable of this, however. In the begining it was on 6 layers, however, they've gotten around it"
Saem, sounds to me like you need to make up your mind.
First yous tate 4 layer PCB's and dual channel DDR dont mix, then you show that they dont mix with RDRAM either - at least at first. And it is now "at first" for DDR dual channel chipsets. Why dont you give them the same range of improvements?
And as for nVidia's stability problems, they are non-existent with the correct DDR config. It doesnt drop in speed unless certain config is used. Sure, this is a BUG. Oh no! I dont doubt it will be corrected..why do you? You seem to shit on DDR constantly for no reason? did JEDEC kill your parents?
As for VIA being crap, you are flat out wrong. As for instability, ha! Read up on current events, and stop judging current hardware absed on years old bugs.
Via isn't reliable, if it was it'd have a bigger presence in the server and workstation market, it doesn't because it can't make it past the rigirious QA. How about you visit a newsgroup with ppl developing linux drivers for Via POS chipsets.
Althornin
25-Feb-2002, 17:39
On 2002-02-25 01:55, Saem wrote:
Via isn't reliable, if it was it'd have a bigger presence in the server and workstation market, it doesn't because it can't make it past the rigirious QA. How about you visit a newsgroup with ppl developing linux drivers for Via POS chipsets.
Thats right, because linux geeks know everything about computer chipsets :smile:
Its called tradition. IT managers will buy what worked in the past, they hate "going out on a limb" with something they havent used before. Trust me, thats where i work, and i see it all the time. they'd rather pay 2 times as much for Intel, not because of stability problems, but because the've always had Intel. Its just like the idea that only macs are good for video editing/photoshop...tradition.
Thats right, because linux geeks know everything about computer chipsets
Actually, these geeks would be reasonable authorities, seeing as they would have worked on more than one chipset from more than one company. ie. they've compared Intel to others and found them lacking. Via, SiS and ALi chipsets suck.
Its called tradition. IT managers will buy what worked in the past, they hate "going out on a limb" with something they havent used before. Trust me, thats where i work, and i see it all the time. they'd rather pay 2 times as much for Intel, not because of stability problems, but because the've always had Intel. Its just like the idea that only macs are good for video editing/photoshop...tradition.
BTW, I know folks who work as net admins and stuff too. I know why they buy and it's usually based on internal QA, they do test Via. Your above statements maybe the case for some but not for all. I know some places that don't have big budgets and they do some of their own -less rigirious- QA on various chipsets and they still find Intel to be the best, out of the usual, Via, SiS, ALi and AMD bunch!
I suppose you haven't figure it out, but why do you think there is an insane amount of revisioning for all those cheapo chipsets, that's because their always cleaning up bugs! They don't release errata because that would show how much ass they suck. They cost less because they don't invest as much into R&D and QA! That's one of the biggest reason Intel products cost more! As for MS not "working" with the other chipset manufacturers because of their releationship with Intel, that's not true. It might have been, but why would MS want to deal with chipsets and their drivers that are revised 10 million times, they've been spoilled by Intel's level of proffesionalism so to speak. Which doesn't revise their chipsets a whole lot and doesn't continaully have to release bois updates to hide some bug, they even make their errata and bugs they find available for PUBLIC viewing. AMD recently started to do the same. But their chipsets still don't come to par with the testing Intel chipsets go through. BTW, why doesn't Dell and the rest sell workstations/servers based on Via chipsets, you know as a second line? They've obviously been through their (IBM's, Compaq's, Dell's) QA. When Via has some bug they throw out a new revision with a few other bug fixes which removes the need for micro code speeds it up a bit do a few other things to make it spiffier and slap an "A" on it's ass and call it new! If Intel had some show stoppers they'd recall the product, that examplifies the significant difference in commitment to quality!
IT IS BECAUSE THEY SUCK!
You may find them to be all right for YOUR home use, but I don't find them to be upto par and neither does the workstation/server market. Everytime I've encountered a Via chipsets I've encountered a problem and I have lots of friends who like to save a buck - that's fine mind you, they save a few bucks I cash in on laughs. :wink:
Sorry, if I'm coming off as condescending, it's one thing to buy Via to save money, but to say it's comparable in quality to Intel is plain nuts. I'm not an Intel zealot, I do believe their hardware is over priced, but I definately too much lower, they wouldn't able to do the great R&D and QA like they do currently. And unlike other companies, they don't have coat-tails to ride on.
Via doesnt have the same quality level as Intel.
It is not because of tradition people dont buy it. It is because they buy or borrow some for test and dont like what they see.
Saem, I would like to add to your point - Another reason why VIA isn't particularly popular in server market is because many net admins make in excess of $50 an hour, and it would cost the company less to buy quality intel motherboard than having their admins spend hours trying to fix cheap VIA crap.
Althornin
27-Feb-2002, 07:06
Sorry, i just dont buy it.
I do work in this area, and i run servers at home, and at my work, on boxes that I built, using VIA and INTEL chipsets.
To say "VIA is crap" is bullshit. To say "VIA is unstable" is bullshit.
You are right that VIA chipsets have more compatability issues, but as long as you stay away from problematic hardware, it all runs like a fucking ROCK.
You can think what you want about Dell and the others, but i tell you the reason they are Intel only shops is that they get a cost decrease/kickback from intel for staying so. Has little to nothing to do with any QA testing.
EDIT: Like you, i dont want/mean to come off sounding condescending (because i plainly think you are foolish, in at least this one aspect) or as some weird "VIA 0wnes j00" freak either. I just think that most of your VIA bashing is based on hearsay and not personal experience. I think your points are invalid and trumped up. While i NEVER said VIA is better than or equal to Intel, you are saying that Intel is infinitely superior to the crap VIA which is bullshit. You guys totally underrate tradition in the role of computers. Most computer geeks tend to blow it off, but when you deal with "normal" people all the time, Tradition rules. Why are macs still the "kings of desktop publishing?" THey aint better...its all tradition.
_________________
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Use Trillian! AOL Sucks.
<font size=-1>[ This Message was edited by: Althornin on 2002-02-27 08:18 ]</font>
I don't know, but it is a fact that VIA needs more driver updates to make things right. I believes many people using Intel chipsets don't have to update their driver.
Btw, I read in Anandtech that Clawhammer has 754 pins. The packaing is not going to be cheap IMHO.
i wouldnt consider via chipsets to be as good as the intel ones.
i have a KT133a and it took me about 6 months (and an inofficial Latancy Patch) to get my SB Live working without constant crashes, my 2nd IDE controller is unusable (possible data loss on my Harddisks).
i dont think my next mainboard will have a Via Chipset
Entropy
27-Feb-2002, 14:18
So this Clawhammer discussion has turned into VIA bashing? Hmmm.
Anyways, yes, 64-bits of DDR PC-2700 memory should seriously hamper the performance of the clawhammer, particularly as it climbs in clock speed. However, it should have a significant latency advantage over the P4 which should be more important for many tasks. It is also reasonable to assume that the memory controller on the Clawhammer will evolve, or have further features enabled with time. It may also be that AMD will improve on-chip caches to help make the core less dependent on the memory bus.
No matter how I try though, I can't see a single 333 MHz 64-bit path as a wise move vs the 533 MHz 64 bit path of the P4. That's just too much of a difference, and in the wrong direction if the Hammer core is as efficient as it seems.
I _still_ haven't seen any authorative statement regarding the clawhammer pin-outs. The Clawhammer has 754 pins out and the Hammer has 940 pins (Athlon has 462). As far as I recall the pin requirements of HT, this difference doesn't cover the needs of 2 HT links and another 64-bit memory controller, implying that the Clawhammer may indeed have hardware support for two channels although this board only implements one. Or, of course, I may be decieved regarding the pin requirements of the Hammer HT links.
I'll try to get this clarified, but if there is someone here who KNOWS, please contribute.
Entropy
Some hammer pics (japanese site): http://www.watch.impress.co.jp/pc/docs/2002/0227/idf04.htm
Any translation? :smile:
Dual Clawhammer configuration is really possible.
Some Ace´s news: Details on AMD's Hammer Demo (AMD)
By Brian Neal
Wednesday, February 27, 2002 2:44 AM EST
We reported earlier that AMD had demonstrated a Hammer-based system yesterday, but at the time there was very little in the way of details regarding exactly what was shown. But now, a great deal more information has been revealed, including several pictures of the demoed systems.
Two Clawhammer systems were shown running various applications, with one system running Windows XP (along with Word and Excel) and the other running a 64-bit x86-64 port of Linux. Both systems were shown to be running various applications, and in the case of Linux, two versions of a simple X11 demo app ran simultaneously, one a 32-bit binary and the other a 64-bit binary. The CPUs are reportedly A0 level silicon and are no more than a month old. The demo systems were not run at full clockspeed, but supposedly they ran at least as fast as other 64-bit CPUs currently on the market (most likely a reference to Intel's Itanium).
A full overview of AMD's Hammer demo can be found here at Anandtech. On the second page of the overview, there are several photographs of the undersides of both the Clawhammer and Sledgehammer CPUs. Clawhammer is reported to have a 754-pin package, while Sledgehammer has a 940-pin package. According to the article, much the the difference is due to the additional HyperTransport channels and the memory interface:
By far the most interesting thing about the CPUs from a physical standpoint is their pincount. The ClawHammer has 754 pins (up from 462 on the Athlon and even up from 603 on the Xeon) and the Sledgehammer has a whopping 940 pins which is just over twice as many as the current generation Athlon.
The majority of the pin increase when going from the ClawHammer to the Sledgehammer is apparently due to the two additional Hyper Transport links and the dual channel 64-bit DDR memory controller vs. the single channel controller on the ClawHammer. Needless to say that manufacturing these things should be interesting.
Apparently, the systems ran on A0 chipset silicon (AMD-8000 chipset) and, as such, the AMD-8151 AGP interface was not functioning properly. The I/O hub worked well, however, so the demo systems ran with PCI video. The reference board itself is a 4-layer design with two DDR SDRAM sockets, one AGP slot, and four 32-bit/33 MHz PCI slots.
Additionally, PC Watch Japan has published an overview (in Japanese) featuring a number of pictures of the Clawhammer and Sledgehammer CPUs as well as the AMD "Solo" reference motherboard for Clawhammer, based on the AMD-8151 AGP graphics tunnel and the AMD-8111 I/O hub (click here for details on the AMD-8000 chipset). In particular, there are some excellent photos of the CPU packaging and sockets.
Thanks to Bluga and KH for the links.
Anandtech Hammer´s article: http://www.anandtech.com/cpu/showdoc.html?i=1591
Althornin
27-Feb-2002, 16:54
Damn, pascal, you beat me to it:) I was gonna suggest we stop bashing VIA and focus on clawhammer/sledgehammer, per anandtechs article.
Looks nice, i want a sledgehammer in my box!
We'll see how perf. pans out...
I agree.
I would like one too, with 1GByte ram (no more VM), an edram 3dcard, dual 17" plasma display, and dolby 5.1 :wink:
But my wife will probably disagree with my little upgrade.
Did you liked the small chip packaging ?
It is cool :cool:
Could this packaging be used to develop a 256bit 3D chip?
Saem, I'm sorry, but your trolling about VIA not being stable is wrong. Dell *DOES* use VIA in one of it's servers.
http://www.dell.com/us/en/bsd/products/model_nasto_2_nasto_715n.htm
If Dell can make it work, it ain't that bad. Intel made people lazy with the 440BX. ALi and SiS are not cheap POS chipset manufacturers, either. Inexpensive they maybe, but it's entirely possible to make a good, solid inexpensive system using one of their chipsets. High performing? Maybe not, but obviously it suits the needs of enough people where ALi and SiS find the chipset business profitable. Quit being such a techno-snob.
Althornin
27-Feb-2002, 19:45
I agree, ben.
And who likes the "musical notes" printed on the clawhammer SOLO motheboard?
Intel jingle at its finest..
http://www.hardocp.com/new_img_02/feb/solo_5note.html
Entropy
27-Feb-2002, 22:19
OK, I'm replying to my own post, but this is as far as my inquiry on Aces' got me.
The first thing I realized after posting was that Anands' article is wrong. The clawhammer does NOT have two HT links less than the Sledge, only one. It has an I/O plus an interprocessor HT link, enabling dual (but not higher) multiprocessing without further glue. I was thrown by the error, and didn't figure out the weirdness immedieately. But there still is something odd going on, as (quoting hattig):
"The pin difference is 186, and that includes one more DDR bus (112 for data and address alone) and one more HT bus (103), which would normally use up 215 pins on their own.
So yes, pins must be shared between either the HT links, or the memory channel links."
And as far as I'm aware an actual implementation of a 64-bit DDR bus could actually take even more.
This is the best model Ive seen though, to explain the pinout. I'm still not happy with the lack of official info.
If, as it seems, the Clawhammer is limited to a 64-bit DDR interface, that's a serious limitation. Wonder what the odds are for affordable Sledgehammer motherboards. :smile:
Entropy
Althornin
28-Feb-2002, 01:01
Well, here's a question:
Because Clawhammer has a HT link for Dual Procs, couldnt a Dual Proc mobo utilize EACH clawhammers DDR controller to link to a seperate 64bit bus? So that its a dual 64bit bus? And then access data from the other bus via the interprocessor HT link?
Or is this implausibly complex, like i think it is?
BenM, I'm not trolling, so STFU with your personal attacks.
As for you absurd theory about high quality for low price, get a clue. It'd be understandable if the price differences were small, but they're not. The fact of the matter is Via, SiS and ALi produce cheap lower quality chipsets because they don't do as much QA as Intel. It doesn't explain all the cost difference it explains a good portion, however.
BTW, back to the troll comment, except for the one Dell bit, all you did is make personal attacks, if your are the yard stick I'm far from a troll.
Oh, yes, here is a little stats lesson for you, a sample size of 1 is worthless. It's very reasonable to say that they are not getting past QA. As for your example, I suggest you scrutinize it, realize that the chipset is rather OLD, what's important is that it's likely been through many hardware/software revisions. Excessive revisioning is BAD!
Saem,
I believe what I said was that SiS, ALi, and VIA make chipsets cheap enough to suit people's needs. I think I did even mention that they are not always top performers.
And by the way, I didn't ask for a stats lesson. I think you have a tough time admitting that you are wrong in your blanket statements.
All right, now for the Hammer.
Any sort of latency advantage that the K8 holds over the P4, isn't important. The P4 and K8 are almost diametrically opposed in design philosphy to compare sub-systems seems -to me at least- pointless. The K8 needs a memory sub-system that keep it fed, not necessarily well fed, but quickly fed, it's clock cycles are worth more than say the ones of a P4 and thus it needs information NOW, not necessarily in large chunks. The P4 with it's deeper pipeline and large instruction buffer won't be as inclined to such a memory sub-system. As you can see, it's kinda hard to say, there is any advantage.
I think this will be a time where a need for a standardized set of benchmarks such as spec, but with far broader code will be needed. This is very much apples to oranges comparisions, the only thing that will be relatable is performance. Also, many will have to put to rest, Spec is a compiler benchmark or SpecFP is far too memory bandwidth sensitive, compilers and memory bandwith are all FAIR parts of the performance equation, when was the last time you ran a program that didn't access any memory at any point in it's execution and it wasn't compiled?
Back to Hammers "skinney" bus, I really don't think it will be a problem, I think the Hammer will be able to use many techniques to use bandwidth more efficently and perhaps even go so far as to implement some really kewl prefecthing algorithms. It'd be interesting to learn whether they've done the aforementioned thing or something better.
Althronin,
I'm not sure about your idea, I can think of one example as to why it would work and one reason as to why it wouldn't.
First the example, I believe PPCs have the ability to share their L2 cache amoung themselves when in SMP configurations.
The reason, if you have 4 processors, how do you figure out which one will have the information you're looking for in RAM, even if you can, could this lead to insane amounts of bus traffic?
Neat thought.
If I understand correctly, each Hammer CPU can link to its own memory. There is a crossbar inside the embedded northbridge which will reroute the memory requests from/to other CPUs.
There is some explanation inside thispresentation (http://www.amd.com/us-en/assets/content_type/DownloadableAssets/MPF_Hammer_Presentation.PDF).
That is correct. The Hammer system architecture is Non Uniform Memory Access (NUMA). Local memory will be faster than remote memory.
Clawhammer will have 2 HT links, enabling 2 way systems. One link on each Clawhammer used to link up to the other CPU, the other link used for AGP, PCI-X. Look at page 40&41 in the above presentation.
Sledgehammer will have 3 HT links for increased connectivity, trivially enabling 4 and 8 way systems.
The system architecture of these CPUs will enable cheap 2, 4 and 8 way systems (compared to today).
Cheers
Gubbi
Dave B(TotalVR)
28-Feb-2002, 13:07
On 2002-02-24 01:27, Dmitry wrote:
It will fail for several reasons:
1) Costs to produce such CPU must be high, and people do not appreciate paying premium price for AMD cpus.The source of expense is the number of pins, hence the packaging.
2) Noone is going to compile programs to take advantage of its propritary 64bit instructions, look, even the intel 64 bit CPU is not doing well.Who says AMD's will do worse? this chip will actually run 32 bit stuff at a decent speed.
3) DDR memory is pathetic.I think not.
4) In order to upgrade to that CPU the poor XP owners will have to replace motherboard, cpu and probably RAM, that in case if AMD wakes up and starts using RDRAM. For intel owners it will be just the matter of replacing the chip.
Well Intel have woken up and dropped RDRAM, they'll have to replace all their kit? well of course they are gonna have to change the CPU and mobo, but why the RAM?
5) Via.
What about em?
Intel only dropped Rambus in the value platforms (for cost reasons) and in the server platforms (for scalability reasons).
The high end P4 workstations will continue to use Rambus.
On Hammer platform cost:
The Clawhammer demoed at IDF was on a 4 layer PCB, which is standard el cheapo stuff.
So one way and two way clawhammers will be dirt cheap (certainly cheaper to produce than traditional 2-way systems).
Also. The HT-to-AGP-tunnel/IO-hub will be so simple to do that even VIA can't fsck it up.
Cheers
Gubbi
More Hammer news from Aces: SledgeHammer and x86-64 Details (AMD)
By Brian Neal
Sunday, March 10, 2002 1:19 AM EST
Thanks to NoSpammer for posting about this article (German) from c't regarding AMD's Hammer demonstration during the recent IDF. The article reports that aside from the two ClawHammer systems, a SledgeHammer system was also shown privately. As we have heard in the past, Andreas Stiller reports that SledgeHammer and ClawHammer are differentiated by a dual-channel and single-channel DDR SDRAM memory interface, respectively. To this end, Mr. Stiller assumes that at least this initial version of SledgeHammer is a single-core processor.
Additionally, first tests indicate that binaries compiled for x86-64 64-bit targets exhibit a 15% increase in performance for a 5% increase in code size. As you know, the x86-64 specification features a larger number of architectural registers: 16 as opposed to 8.
See this german link http://www.ix.de/ct/02/06/070/
This is interesting, seems that x86-64 is considerably smaller boost than I expected, I was hoping for nothing short of 20%, then again, they don't say what compiler they use (most likely gcc). I suppose over the next few months there will be improments to it and an extra 5% will be attainable.
BTW, I learned something interesting, Hammer is built with 9 metal layers as opposed to the K7 and P4 6 metal layers, seems the rather small die size the hammer has is due to the this. But I'm not suprised AMD went this route they only have on advance fab (Dresden) which will be able to initially produce Hammer so die size is one of the most important factors.
AMD has 1 year to optimize the compilers before the Hammer mass market launch. I hope they will do 20% too :)
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