View Full Version : New 3DLabs card anounced...
McElvis
03-May-2002, 13:18
http://www.anandtech.com/video/showdoc.html?i=1614
That sounds expensive...
The filter down approach sounds like a recipe for failure, I doubt its programmable enough to be dropping in displacement mapping or new higher order surface representations as a firmware update.
Humm,
The VPU use a 256bits DDR memory bus 8) :o
Where can I preorder it? :D
Joe DeFuria
03-May-2002, 14:18
Yes, assuming the Matrox Parhelia rumors are correct, this is the second 256 bit DDR based architecture that we'll see this year. That, more than anything else actually, has me very excited. As I was hoping, it looks to me that we are indeed on the virge of starting the "256 bit bus" evolution. A step change in available bandwidth is a "good thing", no matter what architecture we're looking at.
Also, (again, assuming the Matrox rumors are true), I am a little bit disappointed that this is the second "new architecture" that will lack full DX9 pixel shader capability. But if raw performance is significantly higher than the GeForce4 ti-4600 (as it should be with 20 GB/sec bandwidth), it should be a good high-end gaming solution.
Looks to me that this 3D Labs product and the Matrox Parhelia are going to try and compete in the exact same market space.
Joe DeFuria
03-May-2002, 15:37
Hmmm....
I wonder how long it will be before we can see the next-gen cards benchmarked on Doom III:
http://biz.yahoo.com/prnews/020503/laf018_1.html
What I hate about PRs like this, is it doesn't tell you anything about the release date. Doom III will be "debuted" at E3 this year, but what the hell does that mean in terms of how close it is to being finished?
arjan de lumens
03-May-2002, 16:08
Hmmm. 16 scalar FP units (as opposed to, say, 4 vector units) to do the vertex shader job does not sound like a particularly good idea - you get too much latency when doing common operation such as dot-products, reciprocal square roots, exponentiation, etc.
The renderer pipeline programmability? Difficult to judge without looking at the actual instruction set and restrictions like register file size, program size, etc. My initial guess: similar to Radeon 8500, except with support for somewhat longer programs.
4 pipelines sounds a bit low for a design with a 256-bit DDR bus, but then again, if this chip will support >32-bit color and MSAA, as it looks like it will do, it will need every bit of bandwidth it can get. And, given 20 GB/s, probably look quite good.
The total lack of any tessellation/displacement mapping-type features may place the chip at a substantial feature-wise disadvantage relative to Parhelia/R300/NV30, though.
demalion
03-May-2002, 16:18
Why couldn't tesselation processing be done via the vertex processing instructions? We don't know what the instructions (EDIT: and addressing limitations) are to know if this is possible or not, correct?
I can tell you this much about the new Matrox part. it's should compete very well with the GF4 and in some cases beat it out. But these rumored spec on the net are completely false. it's not going to compete with NV30 or anything else released months down the road.
This came from someone that works there. Also, they certainly haven't decide to go tiler or traditional yet.
mboeller
03-May-2002, 16:35
IMHO; this comment was really amazing :
Even more of a surprise is the fact that production quality silicon is currently running at 3DLabs and it would be pessimistic to say that the first shipments of this technology won't occur within 2 months.
I thought Nov/Dec. is the date; but now it seems to be August at the latest!
Joe DeFuria
03-May-2002, 16:44
I thought Nov/Dec. is the date; but now it seems to be August at the latest!
Well, Nov/Dec is/was the date for the consumer based solution. It's not surprising that the professional versions will be out months earlier. The professional version should be in significantly smaller volumes, which will allow 3D Labs to work out the initial "kinks" with drivers and compatibility, and give the fab more time to ramp-up production to be able to handle the larger demand of the consumer market.
Dave Baumann
03-May-2002, 16:46
I thought Nov/Dec. is the date; but now it seems to be August at the latest!
I think its fairly important to take note of this from the first paragraph of Toms preview:
While this architecture is going to find its way initially into the Oxygen line of workstation graphics cards from 3Dlabs, it also heralds some of what we can hope to see coming from Creative Labs this Christmas.
The thing to remember is that the QA process for consumer cards is going to be a lot longer than for the workstation. 3Dlabs are well versed in optimisation for Workstation products, and there are much fewer of them - for consumer boards its likely that 3Dlabs/Creative are starting their dev rel and support from scratch, this could cause some delays to the Creative consumer branded boards.
Joe DeFuria
03-May-2002, 16:52
But these rumored spec on the net are completely false. it's not going to compete with NV30 or anything else released months down the road.
So, which "rumored specs" are false? The only "leaked specs" we have are basically these:
256 Bit DDR Bus (up to 20 GB/sec bandwidth)
Does 8X MSAA as fast as Ti-4600 does 2X MSAA
DX8 compliant
Some DX9 features (like displacement mapping.)
As for it "not competing" with NV30...why not? What do we know of featrues, performance, and price of NV30, R-300, etc? It may not be able to compete purley on features (DX9 support), but features is only part of the story.
Also, they certainly haven't decide to go tiler or traditional yet.
What do you mean by that? Who hasn't decided? nVidia or Matrox? Certainly, they have both decided which architecture (deferred or traditional) for this fall's products. Can you explain what you mean?
Extreme Tech's Preview:
http://www.extremetech.com/print_article/0,3428,a=26271,00.asp
arjan de lumens
03-May-2002, 17:22
Why couldn't tesselation processing be done via the vertex processing instructions? We don't know what the instructions (EDIT: and addressing limitations) are to know if this is possible or not, correct?
A "vertex processor", by Nvidia/ATI definition, is only able to process data already supplied on a per-vertex basis; it cannot in any way create or destroy vertices. In order to do tessellation of any kind, you need to create new vertices. Lots and lots of them. I would think that if the "vertex processor" of the 3dlabs chip was that powerful/general-purpose, it would not have been called "vertex processor" in the first place. And if the chip did have HOS/displacement mapping functionality, they would almost certainly make a point out of it in the presentation that has been given out.
And if the chip did have HOS/displacement mapping functionality, they would almost certainly make a point out of it in the presentation that has been given out.
Taken from the above ExtremeTech link:
Higher Order Surfaces: N-patches, Bezier, B-Splines, NURBS
So it looks like the P10 does support it. Now how well will its n-patchs be compatible with ATI's truform?
Joe DeFuria
03-May-2002, 17:58
No displacement mapping mentioned, but from ExtremeTech's preview:
Higher Order Surfaces: N-patches, Bezier, B-Splines, NURBS
On displacement mapping: I've stated my opinion on it in another thread, and it's relevant here:
I don't think displacement mapping will be anything more than a "gimmicky" feature for the next couple years. I see the current implementations displacement mapping as being analogous to "bump-mapping" support back in the DX6 era.
By the time developers start to take displacement mapping seriously, I'm betting we'll be on DX 10/11 hardware, with vastly superior and more general implementations. Until then, I predict we'll only see a smattering of games with limited and "gimmicky" support for displacement mapping in. (Similar to how various forms of bump-mapping were supported in the past, to be soon superceded by more general pixel shaders.)
Joe,
So, which "rumored specs" are false? The only "leaked specs" we have are basically these:
These are the leaked specs that i'm talking about. They showed up today...
http://www.nvnews.net/forum/showthread.php?s=567b87a4c3548ddb88ece335a32d79e4& threadid=14216
I don't believe what's written there, do you?
As for it "not competing" with NV30...why not? What do we know of featrues, performance, and price of NV30, R-300, etc? It may not be able to compete purley on features (DX9 support), but features is only part of the story.
Why not? Since I was told was that it's going to compete in features/performance with the Geforce 4. I was told it's roughly the same speed and a little faster in some cases. Unless you think the Geforce 4 would compete nicely in features/performance with NV30 that is? If that's your opinion, all i can say is that I wouldn't agree and leave it at that.
Well joe, since we mainly have rumored feautres/performance of this matrox product to compare against each other, I wasn't talking about price. i wasn't told anything about the price. although they do have a price on this rumor page, and it does compete with the GF4, if you want to believe it that another story...
What do you mean by that? Who hasn't decided? nVidia or Matrox? Certainly, they have both decided which architecture (deferred or traditional) for this fall's products. Can you explain what you mean?
I was talking about matrox. When i inquired about it being a tiler or traditional, the guy I spoke with said they haven't made the decision to go with a full blown tiler or stick with the traditional down the road. He was pretty vague as you can tell, and didn't really answer the question about this product. he said that they (matrox) keep changing their minds (and or direction) and since we have heard rumors of this being a tiler, I thought i'd add that.
arjan de lumens
03-May-2002, 18:36
And if the chip did have HOS/displacement mapping functionality, they would almost certainly make a point out of it in the presentation that has been given out.
Taken from the above ExtremeTech link:
Higher Order Surfaces: N-patches, Bezier, B-Splines, NURBS
So it looks like the P10 does support it. Now how well will its n-patchs be compatible with ATI's truform?
Hmm. The same chart says that Geforce4 supports Bezier and B-spline surfaces, which is news to me at least. (AFAIK, early Geforce3 drivers exposed driver-level support for such surfaces, but that was later removed.)
If N-patches are supported by the drivers for this card, I would expect the result to be 100% compatible with the ATI implementation - N-patches aren't that ill-defined.
Oompa Loompa
03-May-2002, 18:53
As I was hoping, it looks to me that we are indeed on the virge of starting the "256 bit bus" evolution.
Nasty Freudian slip, that.
Gunhead
03-May-2002, 18:58
Funny, but the inclusion of lots of simple all-purpose processing units reminded me of Fuzion 150. (Albeit it was designed to have 1.5k of them and not much else on board.) Even the transistor counts (76M) match. Wonder if 3DLabs has taken peeks into network processors (NPUs? :P )? Then again, 3DLabs wasn't pimping ImageBR so maybe they don't want an NV1 of their own after all :P
BTW, reading Anand's text, did anyone happen to get the impression that 3D is quite not his strongest area? Would have to bother to read again to give precise quotes, so I won't bother, but it's just too bad it wasn't somebody from B3D making the visit and getting all that data...
LeStoffer
03-May-2002, 19:21
Hmmm: transistor count 76M + process technology 0.15 micron + 4 pipe lines = me thinks that this baby won't be a killer in raw fillrate. Sure it'll have the ability to apply 8 textures in a single pass, but I guess that this will mainly be exposed through OpenGL 2.0 (or 3Dlabs GL-extentions that is).
If the GF4 or 8500 were extremely limited by memory bandwidth the consumer part would be awesome, but this is not the case. So I guess the extra bandwidth will be used for FSAA/better image quality - not ultra high FPS. But we'll see for sure 8)
Joe DeFuria
03-May-2002, 19:30
Quincy,
These are the leaked specs that i'm talking about. They showed up today...
You need to get out more. ;) That .jpg showed up this past April 1st. They are known to be a hoax.
...Since I was told was that it's going to compete in features/performance with the Geforce 4.
And I've been told its features may compete with GeForce4, but performance would be in another class. So we each have our sources saying different things. Please, don't tell me that "your" sources must be better, because such an argument would be pretty meaningless. ;) You'll have to forgive me if I don't put much faith in your sources if you consider this jpg to be a "credible" rumor, when it's been known for a month to be a hoax.
Again, the "credible" rumors (oxymoron?) about Parhelia is what I mentioned above. They indicate a new class of performance, but not a new class of features.
I was talking about matrox. When i inquired about it being a tiler or traditional, the guy I spoke with said they haven't made the decision to go with a full blown tiler or stick with the traditional down the road.
I'm still not clear on what your trying to say in terms of relevance to Parhelia: Did this contact of yours simply refuse to tell you that Parhelia is a deferred renderer or a "tradtional", or is he saying that Matrox hasn't made up their mind on it yet? If you're talking about products after Parhelia, what's the relevance to our discussion?
Joe,
You need to get out more. That .jpg showed up this past April 1st. They are known to be a hoax.
i do get out, which is why I hadn't seen it ;) Anyway, I was saying that i didn't believe it a few posts back for the record.
And I've been told its features may compete with GeForce4, but performance would be in another class. So we each have our sources saying different things. Please, don't tell me that "your" sources must be better, because such an argument would be pretty meaningless.
My sources are bigger than yours :wink: don't worry, I wasn't going to bother arguing that. It would be a waste of time.
You'll have to forgive me if I don't put much faith in your sources if you consider this jpg to be a "credible" rumor, when it's been known for a month to be a hoax.
Actually i didn't consider this jpg to be credible. That why I said:
"But these rumored spec on the net are completely false"
I'm still not clear on what your trying to say in terms of relevance to Parhelia: Did this contact of yours simply refuse to tell you that Parhelia is a deferred renderer or a "tradtional", or is he saying that Matrox hasn't made up their mind on it yet? If you're talking about products after Parhelia, what's the relevance to our discussion?
He didn't refuse, but he just didn't answer my question directly. He was also on his way out, so i didn't get to ask anything else. I think it's a safe bet that this new product won't be a tiler and will stick with a more traditional design, which is what i was getting at with this comment. if they haven't decided what they are using after this product, kinda makes me think they would stick to something they are familiar with.
Mintmaster
03-May-2002, 20:47
Hmmm: transistor count 76M + process technology 0.15 micron + 4 pipe lines = me thinks that this baby won't be a killer in raw fillrate. Sure it'll have the ability to apply 8 textures in a single pass, but I guess that this will mainly be exposed through OpenGL 2.0 (or 3Dlabs GL-extentions that is).
If the GF4 or 8500 were extremely limited by memory bandwidth the consumer part would be awesome, but this is not the case. So I guess the extra bandwidth will be used for FSAA/better image quality - not ultra high FPS. But we'll see for sure 8)
The extra bandwidth seems like it would be useful if you wanted to forego all the funky memory architectures that NVidia and ATI are using, like the "crossbar memory controller" and the caches that they have. This could save silicon for the other things they have on the chip. Just a guess though.
Joe DeFuria
03-May-2002, 21:01
"But these rumored spec on the net are completely false"
Right, but my point is, (most) everyone already knows that the ".jpg" rumors on the net are completely false. The jpg does NOT represent the "rumored" performance of Parhelia. The "rumored specs" that most people are put some faith in, still show a significant theoretical performance advantage compared to the T-4600.
In short: no one is expecting Parhelia to have specs similar to the .jpg: However, most are still expecting Parhelia to have performance notably higher than Ti-4600.
Of course, one still has to factor price into the equation. I do exect the "high end" Parhelia to significantly outperform the ti-4600. But I also expect it to cost significantly more. It may very well be the case that a Parhelia based product that is targeted at similar price points as the Ti-4600, will have a similar performance.
Mephisto
03-May-2002, 22:08
[quote=arjan de lumens]
So it looks like the P10 does support it. Now how well will its n-patchs be compatible with ATI's truform?
Well, TruForm is nothing more than the marketing term for N-Patches ...
LeStoffer
03-May-2002, 22:09
Mintmaster:
The extra bandwidth seems like it would be useful if you wanted to forego all the funky memory architectures that NVidia and ATI are using, like the "crossbar memory controller" and the caches that they have. This could save silicon for the other things they have on the chip. Just a guess though.
Good guess! 8) You would also bypass some of the driver-nightmares that it would be to optimize for a totally new chip with a driver team that have all kinds of other important tasks on their hands.
In that regard it could be even more brute force than ATI and Nvidia. If it is, it won't be received well here! :P
Dave Baumann
03-May-2002, 22:20
Personally I'd think the opposite - the extra wide bus probably highlights the need for crossbar controllers even more, as now there is more bandwidth available to waste.
arjan de lumens
03-May-2002, 22:29
Personally I'd think the opposite - the extra wide bus probably highlights the need for crossbar controllers even more, as now there is more bandwidth available to waste.
Good point. With 200+ processors, apparently all capable of accessing random memory across the bus (!!), you would want to segment it into as many small buses as practically possible. A 256-bit data bus with only a single address bus does not have nearly the address bandwidth that a chip like this is going to need to function optimally.
LeStoffer
03-May-2002, 22:44
Personally I'd think the opposite - the extra wide bus probably highlights the need for crossbar controllers even more, as now there is more bandwidth available to waste.
You're right of course. :oops:
So what are we going to use all this nice bandwidth for? Supersample FSAA? Anisotropic filtering? Making sure that minimum FPS stay high enough (no choke point)?
On a sidenote: I cannot believe that I ask this question given the discussions about bandwidth there were back in the GF SDR/GF2 GTS days! That was the time where Bitboys had all the answers. Now all the buzz about large on-die memory seems, well, off. :roll:
Oki, that P10 thingy looks sorta interesting but...
"The P10 will be first made available very soon on a 3DLabs card aimed at the professional market.
Dunno but this implies it won't be available as a consumer grade card "soon".
" Creative will take the P10 technology and tailor it to the specific needs and requirements for the gaming market. The P10 will then be found on Creative Labs branded boards that will sell at prices competitive with the GeForce4"
Well, that statement is giving me the creeps. What does "tailor to the specific needs..." mean? I thought it was some sort of widely accepted truism that 256bit solution will be expensive, no? But still, pricing is supposed to be competitive to 128bit boards.
So maybe the "tailored" consumer board will be dumbed down to 128bit in order to be competitive?
Very interesting hardware, too bad it's not fp all the way through the pipe...
I remember reading an NVidia PDF a while back which mentioned that another programmable stage should be added to the current set :
a primitive processor (handling tesselation of HOS, possibly displacement mapping?, etc...).
This seems to be the one thing missing from 3dlabs architecture.
I also wonder if their programmable pixel processor is general enough to do things like SuperScene AA, or Z3 AA...
It's a little early to tell how good this chip is (it really depends on how programmable their individual units are), but I can't wait to see more detailed specs.
I also can't wait to see what exactly DX9 is - rumors seem to indicate it's a small step from DX8.1... then there is DX9.1 which is supposedly a large step from DX9.0? Too much rumor is flying...
For instance, 3dlabs is saying that pixel shader 2.0 support is unlikely this year (requires too many transistors). But then DX9 is (supposedly) coming out this year, and r300 will be announced right after, with NV30 announced in August.... errr what the hell is going on?
Is DX9 likely to be out before August?
Serge
Dave Baumann
03-May-2002, 23:36
http://www.vr-zone.com/Home/news142/3DLabs-16.jpg
Nice flow charts DaveBaumann. But could you clarify something why are they using scalar SIMD units? What advantage do they hold over vector based, isn't 3D image processing more vector based and thus it'd be a more optimal solution to got with VUs or are there implementation costs involved here?
I realize that one can use vector based SIMD units in a scalar fashion, I have a feeling it can go the other way around as well.
PrzemKo
04-May-2002, 00:12
Me wonders about one more thing: why 10-bit RAMDAC? are they going for larger colour space, or is it just for mixing multiple AA buffers, like in Voodoo 5? And is that part flexible enough to run things llike hmmm... a full game engine (gfx part at least)? I could also imagine stuff like one-chip game console (not counting memory, perhaps also sound chip), a pc without x86 CPU or next-gen x86 with integrated bunch of P10-like gfx units.
Other my concern is that whether they went too far ahead - they will pay most of development price while their followers will get most profits (sadly it is a basic law of economics).
Anyway, it's good to have 3D scene back among the living.
LittlePenny
04-May-2002, 00:18
The addition of Virtual Memory is phenomenal is my opinion. It should allow for more software sorting of how things in the vid card memory will be stored, so while having the extra traces for a crossbar would be nice, I don't think it would be as necessary with this new feature.
Saem,
Acording to anandtech, this is why: http://www.anandtech.com/video/showdoc.html?i=1614&p=5
Regards / ushac
The P10 is a definitely a forward looking architecture. I would prioritize its major contributions as follows:
1. The virtual memory model for texture access (actually its technically a L2 caching mechanism). I have been waiting for this to come to the consumer scene for some time. Unfortunately its most significant benefits won't be felt until there is a reasonable install base using it.
2. The 256 bit external bus. This is one of many near term memory bandwidth options. BGA packaging has made this particular memory bandwidth option interesting to several vendors this year. As I mentioned earlier, the chips coming out in the DX9 time frame should all have enough memory bandwidth to meet their needs. When it comes to transistor count though; well that's another story. An end-to-end floating point pipeline takes a lot of transistors. The companies that come up with creative ways to significantly increase their total transistor count over their competitors will have the leading edge as the competition heats up.
3. The flexibility afforded by their programmable architecture. In some sense 3DLabs benefits the most from this architecture (making it easier to provide functionality) while programmers and users see the benefits mostly indirectly. What I like about it the most though is the direction it is headed in.
phynicle
04-May-2002, 05:35
once it makes itz way down to the gaming market creative labs will probably cripple the bus width and turn it back into 128 to save cost and so on....
another thing like all good hardware it needs support without the industry support alll their features are going to be a waste even in games, which i'm sure will benefit alot but i doubt developers will tailor their games just for 3d labs card, remember money is their main target and they want to sell their games to as wide of a market as possible...which is sometimes a sad fact just imagine how much better games will look
3DLabs is talking about the general programmability of their architecture, and that you could theoretically run a general purpose application on it.
Since it's that general, it'd be interesting to know whether they'll be more forthcoming with handing out the (register-level) programming documentation for their shiny new architecture. If they do this, the card could be a godsent for those of us who are interested in (non-Linux) alternative operating systems.
Greetings, Christian
Tygrus_Artesiaoa
04-May-2002, 08:46
I don't know if anyone remembers Permedia 3...
I actually thought it was kinda neat when it came out but it was not a gaming chip...it could game but rather it is/was a good CAD cheap 3d pro card.
Anyways when it came out was when 3dlabs announced virtual texturing support for 256mb and that it was seemless. That it used its dma engine to page out textures I think in 4k blocks...and would allot as needed.
Bear in mind the vx1 is without the glint geometry processors.
The Oxygen cards are not the equals of the wildcat cards...inherited by name from Intergraph.
All the oxygen cards support virtual texturing as well.
Dave Baumann
04-May-2002, 08:54
I may be going to see 3Dlabs next week for the P10 presentation they gave out in the US, however I'll be a little armed with more knowledge - so if there are any questions you want answered then post them in this thread (http://216.12.218.25/domain/www.beyond3d.com//forum/viewtopic.php?p=10165#10165) (so this thread here can remain a discussion on the technology).
3DLabs new tech looks like something that I was expecting from them...
now we have ATi, Nvidia, Trident, SiS and 3DLabs supporting DX8.x and looks like Matrox wants to sign in to this group too. :)
But how long it is going to take before developers begins to get their DX8.x based games out? at least it looks like that in HW DX7 is left behind and everyone even in mainstream and laptop markets are getting to DX8...
Does the P10 have an bandwidth saving features like Nvidia has such as Z-compression, crossbar memory, etc? If not, then that 256 bit external bus sounds a lot less impressive. Anyone have any idea how useful Nvidia's compression methods are in actual real world games?
demalion
05-May-2002, 16:01
Why couldn't tesselation processing be done via the vertex processing instructions? We don't know what the instructions (EDIT: and addressing limitations) are to know if this is possible or not, correct?
A "vertex processor", by Nvidia/ATI definition, is only able to process data already supplied on a per-vertex basis; it cannot in any way create or destroy vertices. In order to do tessellation of any kind, you need to create new vertices. Lots and lots of them. I would think that if the "vertex processor" of the 3dlabs chip was that powerful/general-purpose, it would not have been called "vertex processor" in the first place. And if the chip did have HOS/displacement mapping functionality, they would almost certainly make a point out of it in the presentation that has been given out.
That's just it...this isn't a "vertex processor" by the nVidia/ATi definition. I think it is too early, especially given indication that this press release was early for some reason according to some of the articles, to make an assumption. I'm just asking why you would assume it can not at this point? It seems, if the addressing flexibility and register referencing goes even further than PS 1.4, for example, (which seems a given from the information given), more likely that tesselation is possible than it is not.
From the press release:
In addition to running all of today's workstation and mainstream 2D and 3D programs, new applications are expected to soon emerge that use advanced techniques including, but certainly not limited to:
* Real-time wavelet-based geometry and texture decompression engines that enable reduction in the size of terrain models up to 100 fold;
If it can do that kind of stuff in hardware it must be very flexible. Sounds to me like it could very well do HOS.
Regards / ushac
mboeller
06-May-2002, 07:48
That's just it...this isn't a "vertex processor" by the nVidia/ATi definition. I think it is too early, especially given indication that this press release was early for some reason according to some of the articles, to make an assumption.
IMHO could very well be the impact of Matrox's new card. Maybe they will compete in the same highend workstation market.
ah... GFX market is getting exciting again. :)
Joe DeFuria
06-May-2002, 13:52
IMHO could very well be the impact of Matrox's new card. Maybe they will compete in the same highend workstation market.
While I believe that the new Matrox part and the P10 will be more or less direct competitors, I think the reason for the "rushed" announcement has more to do with the Creative Labs acquisition. (One of the previews alluded to this.) There is, I believe, some point in the process where the companies involved must enter a "quiet" period until the acquisition is legally complete.
It's likely, IMO, that if 3D Labs didn't announce it last week, they would probably be unable to legally announce it for a couple months.
Joe: It is nice to see first how this "new" high end can battle against each other and when the DX9 HW arrives, it will be interesting see, if Dx9 cards are able to be faster than these. (DX9 shaders are said to be very transistor hungry, so I presume that number of them could be lower than in 3DLabs and Matrox counterparts. But maybe 0.13µm changes that...)
How about memory bandwidth figures and FSAA implementations?? Of course feature set will pass these, but when ppl are going to get some programs that uses those new features?
wheeh.. following 3 quaters should be something really interesting to watch... :)
if DX9 HW is slower than "new high end", it will definately cause some hair lose in some CEO's rooms. :)
and about a Matrox... old 3dfx'ers, don't rush with GF4Ti's... I know that you love good FSAA with minimal performance hit and good Image/Texture Quality. ;)
well, afaik, Matrox G400 had one of first Anisotropic filtering implemtations in consumer level, so I think they keep pushing it forward. (I don't exactly know about it in their next gen though.)
I can't remember right now 100% sure how Aniso works, but if I am right, Number of TMUs (in non-memory-bandwidth-limited situation.) is much more important with Aniso than number of pipelines... if this is true, then I don't think there is much problem with it.
But I think that Matrox will not release only chips this time... I think we see some benches on very same day when NDA is lifted. And you don't need to be heavy surfer to notice that day must be close.
too many sources are stating the same day.
Well Nappe1, a core that can only fetch 8 texels per clock and TMU will not really shine in the texture filtering area performance wise.
Well Nappe1, a core that can only fetch 8 texels per clock and TMU will not really shine in the texture filtering area performance wise.
You must double that numbers of texels ... ;)
and then again remember that they have massive amount of bandwidth to consume.
I don't think so. Don't forget trilinear ;)
Though the bandwith will certainly help, but at least the NV20 core is more fillrate than bandwith limited in case of high degree anisotropic filtering.
Ram: well, only way to find out it is wait and see...
I can't be 100% sure about my infos either...
Few things:
- The 256bits bus will help with high sustained fillrate with next-generation games like Doom3. IIRC GF3 was only capable to do 30 fps (no aniso, compressed textures), my guess it means only sustained 600MTexels. This new 3DLabs chip has the potential to be three times as fast.
- This new chip dont need a 4 way crossbar because it use a tile (8x8) increasing the 2D spatial locality hit rate. There is no need of 64bits access to the framebuffer. With clever design of the caches a 2 way could be enough.
- It maybe used as a advanced image processor.
It is like life, everyday something new happens, and this is good news. This card has speciall potential because of the many professional applications it may have: CAD, Architecture, Medicine, etc...
Kudos to 3DLabs for their hard work.
bump
Something is not working with this forum.
Dave Baumann
08-May-2002, 17:19
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