R520 Infomania

[russo121]

I think this is nothing new to what was speculated but.... there it is: http://www.techpowerup.com/reviews/Cebit2005/Day4/5 :P

PS: I want this baby!!

[wireframe]

Who wouldn't want "this baby"? Heh. Can't wait to get my paws on one. I really like the bit about 10-bit per channel. Basics like these can go a long way. The sooner they launch it the better. :D

[Geo]

Yowza, $600-700? I imagine that is a combination of 512mb and SLI's proof of the market that is willing to spend in that range (and higher).

I'll be very interested to see how next gen compares to this gen-SLI'ed, and what if anything that does to the SLI market going forward. Tho this gen of SLI got a bit of a late start compared to the cards that are running it.

I guess what I'm saying is that at least some loud mouths will finally have the cold water dashed in their face of having a $5-600 card kick their ass all over the lot with better compatibility when they paid $1k or more for their SLI setup just a couple months before. That's not entirely fair to SLI for a few reasons, including the timing issue of SLI coming in much later than original release of the cards. I'm just saying those folks will be out there squawking and it will be interesting to see if they affect the market or not going forward. I think 'not', or 'not much for not long', but we'll see.

[wireframe]

Yowza, $600-700? I imagine that is a combination of 512mb and SLI's proof of the market that is willing to spend in that range (and higher).

Doesn't sound that bad at all as long as that is the actual street price and not $700 + 30%. People paid that for the current top cards and I was very close to that for mine.

[IbaneZ]

So this time we'll get the EXTREME pipes then. :)
24x1.3=oh baby!

I dunno folks, i think it sounds a little too good to be true. But i'm gonna be the first in line to buy one anyway. I'll be happy if it's faster than a 600/595 MHz X800 XT PE. :lol:

[loekf2]

So this time we'll get the EXTREME pipes then. :)
24x1.3=oh baby!

I dunno folks, i think it sounds a little too good to be true. But i'm gonna be the first in line to buy one anyway. I'll be happy if it's faster than a 600/595 MHz X800 XT PE. :lol:

Yikes..... and:

"The most important architectural change is support for WGF 1.0 (Windows Graphics Foundation). This is the successor to DirectX9, often called DirectX Next. WGF will be included as standard in Microsoft Longhorn.
WGF offers new exciting features for game developers like "unlimited" shader length, Geometry Shaders, Much lower overhead than DirectX9 and many more."

Please correct me if I'm wrong but I thought that WGF 1.0 = unified shader models, or is Microsoft saving this for Longhorn 2.0... released in let's say 2025.

I thought we all agreed here that R520 is yet another spin of the R3xx (m)architecture.

[digitalwanderer]

I thought we all agreed here that R520 is yet another spin of the R3xx (m)architecture.
Yup, but that doesn't mean that we were all correct. ;)

[martrox]

I find this hard to believe.... but, if true....... May need to take out home equity loan......

[digitalwanderer]

I find this hard to believe.... but, if true....... May need to take out home equity loan......
It definately would be incentive for me to build meself a PCIe system at least! :?

[Kombatant]

I thought we all agreed here that R520 is yet another spin of the R3xx (m)architecture.

Since when does one invalidate the other? :?:

[Xmas]

So this time we'll get the EXTREME pipes then. :)
24x1.3=oh baby!

I dunno folks, i think it sounds a little too good to be true. But i'm gonna be the first in line to buy one anyway. I'll be happy if it's faster than a 600/595 MHz X800 XT PE. :lol:

Yikes..... and:

"The most important architectural change is support for WGF 1.0 (Windows Graphics Foundation). This is the successor to DirectX9, often called DirectX Next. WGF will be included as standard in Microsoft Longhorn.
WGF offers new exciting features for game developers like "unlimited" shader length, Geometry Shaders, Much lower overhead than DirectX9 and many more."

Please correct me if I'm wrong but I thought that WGF 1.0 = unified shader models, or is Microsoft saving this for Longhorn 2.0... released in let's say 2025.

I thought we all agreed here that R520 is yet another spin of the R3xx (m)architecture.
WGF 1.0 = DirectX Graphics 9 for Longhorn basically, WGF 2.0 is the new stuff. So R520 won't be beyond DirectX9.0c.

[Goragoth]

According to the article the ATi SLI won't be limited to 2 cards. I just have to wonder if there will be some crazy Alienware box with 4 of these babies in it. Now that would be certifiably insane :shock:
Just one of these would be quite nice though... no I think it would be very nice actually :) I guess we'll see how things shape up pretty soon but I know a lot of people here have been saying that there is no way we'll see a 2x speed jump in this next generation. It would be nice to see them proven wrong (I doubt they'll mind :wink: ).

[Dave Baumann]

On the face of things there are going to be some disappointments.

[digitalwanderer]

I just have to wonder if there will be some crazy Alienware box with 4 of these babies in it. Now that would be certifiably insane :shock:
And can ya imagine the pricetag on that sucker and how nice a monitor you would need to utilize even a fraction of that power?!?!? :shock:

[Ostsol]

On the face of things there are going to be some disappointments.
Regarding the R520 or ATI's multiple video-card solution?

(I'd rather not use SLI as the all-encompassing term.)

[russo121]

Imagine that 1 r520 will be faster than nvidia sli setup and (I hope) less expensive than 2 nvidia cards. Now imagine the same thing in an AMR setup.... it will blow any biggest score in the planet. 8)

On the face of things there are going to be some disappointments.

Disappointments to people that bought sli nvidia cards, or, people speculating too much here?

[Ostsol]

Imagine that 1 r520 will be faster than nvidia sli setup and (I hope) less expensive than 2 nvidia cards. Now imagine the same thing in an AMR setup.... it will blow any biggest score in the planet. 8)
Now imagine NVidia's inevitable reply. :wink:

[digitalwanderer]

Disappointments to people that bought sli nvidia cards, or, people speculating too much here?
From my years of Davespeak study I'd have to say he was implying that we were all getting our hopes up just a wee bit much and that if we continued to do so we would be disapointed in the final product.

Also, whenever I hear the term "extrememe pipelines" now or any variation on that theme I just have this humongoid bullshit alarm that goes off.... http://66.224.5.66/board/images/smilies/bleh2.gif

[MuFu]

I think this is nothing new to what was speculated...

Indeed. Wrongly speculated at that.

[trinibwoy]

WGF offers new exciting features for game developers like "unlimited" shader length, Geometry Shaders, Much lower overhead than DirectX9 and many more."

Couple questions:

1. Does anybody know what changes were made to reduce the DirectX overhead?

2. Why is ATI's tiling approach more efficient than the straight screen split method Nvidia is using?

Would be nice to see what two X900XL do in AMR,MVP or whatever. :)

[digitalwanderer]

Why is ATI's tiling approach more efficient than the straight screen split method Nvidia is using?
I'm not sure about ATi's specific implementation, but I thought tiling in general was more efficient than the SS method nVidia is using.

Splitting the screen top/bottom's biggest drawback can be found in scenes with skyboxes, the top-halves load is generally a hella lot lighter than the bottom-halves load.

Tiling tends to mix it up with an evener split, I thought.

[trinibwoy]

Why is ATI's tiling approach more efficient than the straight screen split method Nvidia is using?
I'm not sure about ATi's specific implementation, but I thought tiling in general was more efficient than the SS method nVidia is using.

Splitting the screen top/bottom's biggest drawback can be found in scenes with skyboxes, the top-halves load is generally a hella lot lighter than the bottom-halves load.

Tiling tends to mix it up with an evener split, I thought.

That makes sense for a fixed 50/50 split but with the adaptive load-balancing algorithm Nvidia has in place it should be distributing the load pretty evenly. My guess is that tiling does not require this extra load balancing logic in the driver which may reduce overhead somewhat. Guess we'll know when we know.

[digitalwanderer]

Guess we'll know when we know.
Yup, until then it is all just speculation/silly season. :)

[ANova]

I still think the most of this is being overblown. I doubt 2x the performance.

[Xmas]

WGF offers new exciting features for game developers like "unlimited" shader length, Geometry Shaders, Much lower overhead than DirectX9 and many more."

Couple questions:

1. Does anybody know what changes were made to reduce the DirectX overhead?
Please don't attribute that quote to me... too much marketing speak for my taste :D

For the driver model changes, see this Powerpoint presentation:
http://download.microsoft.com/download/1/8/f/18f8cee2-0b64-41f2-893d-a6f2295b40c8/DW04018_WINHEC2004.ppt

That makes sense for a fixed 50/50 split but with the adaptive load-balancing algorithm Nvidia has in place it should be distributing the load pretty evenly. My guess is that tiling does not require this extra load balancing logic in the driver which may reduce overhead somewhat. Guess we'll know when we know.
Not much guessing involved here, actually. The advantage is the load balancing, and it comes at the price of very slightly less spatial coherence. And since the frame buffer requirements are constant, it's possible to save some memory on each card.

[g__day]

Get the feel it will once more be a case of the hardware being a long, long way ahead of scalable game software that can utilise its performance? The old chicken and the egg problem.

I expect by Q3 for someone to demo an insane water cooled / peltier rig that is 2 dual CPUs - say 4GHz each by marketing figures + 2 * next gen-GPUs + emergent PPU and say 2GB of insanely fast memory. And apart from scoring 20K in 3dM05 - so what? What game yet needs this level of h/w grunt? How dated will such a rig be by the time games come out that support this level of rig figuring it as a typical mainstream set-up?

It will be interested to see if Cell, Xbox 2 - and PS3 help push gaming along so that we do see a transformation jump in the scalability of graphics quality to cater for next generation chips. But I won't hold my breath just yet...

What software to folks here think will mostly be used to demonstrate the power of these rigs? Dreaming of Quake 3 at 1,000 FPS just doesn't do it for me anymore.

[digitalwanderer]

Get the feel it will once more be a case of the hardware being a long, long way ahead of scalable game software that can utilise its performance? The old chicken and the egg problem.
I'm still looking for a game to give my X800TT a serious run for it's money! :lol:

[kemosabe]

On the face of things there are going to be some disappointments.

Thread-killer. :?

[Tim Murray]

Wow. I've never seen such total bullshit in my life.

"It's a 24-pipe card THAT IS EVEN MORE THAN 24 PIPES AND HAS HIGHER CLOCKS! AND IT SUPPORTS MORE STUFF! AND IT'S THE BEST CARD EVER!!!1111omglolz"

You all realize that this kind of crap comes out every time a new chip is coming out, right?

[Farid]

This sounds great, we have the obligatory "several insider sources", we have the, now classic, "Extreme pieplines" and we have the "twice faster than previously released X card". We definitely have a lot of the right ingredients for one of thoses, always ressourceful, 20 pages BS speculations thread.

Now, this thread lacks some essential elements, such as the "Ati has something big up their sleeve, can't say anymore" card, we also need some insider tidbits provided by someone who act like he's in the know, but he, in reality, is full of it. And only then, we'd be able to consider this thread a "good one".

Never mind me, I'm just kidding, but, seriously, 1.3 pipelines? :lol:

What's suppose to be a 1.0 pipeline? Or a 0.8 pipeline, for that matter?

If an architecture has more ALU per pipes, that doesn't turn them into 1.3 "extreme pipes". It's still one pipeline.

BTW, if Ati use a new architecture on their pipes, what would be the point to have 24 of them?

[Tim Murray]

Vysez, I love you for posting at EXACTLY the same time as me. And saying what I said, only longer. :D

[Farid]

Vysez, I love you for posting at EXACTLY the same time as me. And saying what I said, only longer. :D
Damn, you're blazingly fast... You must have strong typing skills [Think 1.3 today's typing skills]. :P

[Tim Murray]

Vysez, I love you for posting at EXACTLY the same time as me. And saying what I said, only longer. :D
Damn, you're blazingly fast... You must have strong typing skills [Think 1.3 today's typing skills]. :P
I blame the keyboard from 15 years ago (okay, it turns 15 on May 29). The IBM Type-M is 1.3 times today's keyboard.

(oh my god this 1.3 thing can't end well)

[Geo]

This isn't an anonymous forum posting somewhere --this is a sizeable website posting it as a major original (i.e. its theirs, not a repost) news item for which they are claiming to be the ones who dug up the info --and they are claiming to have done so as part of a major industry show where it can be assumed that there were at least a few attendees who did in fact have this kind of info. This puts the sites credibility on the line in a way that joe blow's forum post can never do. Me, I don't know this site and their reputation, but I can see why people would at least be wondering if there is some credibility here compared to joe blow's forum post. . .

[Pete]

Would it be so wrong for me to predict the R520 will be 1.3x as fast as the X850XTPE, regardless how many pipes it has? :P

[kemosabe]

BTW, if Ati use a new architecture on their pipes, what would be the point to have 24 of them?

Sorry, but why would a different architecture preclude an increase in the number of pipes? NVDA changed their architecture from NV30 to NV40 and quadrupled the pipelines. I don't see any necessary relation.

[LeGreg]

This isn't an anonymous forum posting somewhere --this is a sizeable website posting it as a major original (i.e. its theirs, not a repost) news item for which they are claiming to be the ones who dug up the info.

Yep.. dug up themselves in forums and on the inquirer.

This puts the sites credibility on the line

what credibility ?

[Hellbinder]

He was not saying each pipeline was = to 1.3 pipelines. Simply that its more like 1.3 pipelines.

this is a simple concept.

For example. The Savage 2000 had 2 pipelines but 2 extra partial TMU's that greatly ingreased its performance in situations where they were advantageous. Like, Q3 and UT using METAL.

In this case we are not talking about "Extra TMU's" but something else. The principle is the same.

Dissapointed in final Clock speed and possibly the Full WGF stuff. Surley not the Pipeline Design hint and the performance hint. In several Key areas it should be 2x as fast.

[kemosabe]

You're disappointed with a rumoured 700MHz core clock?? :shock: :lol:

[caboosemoose]

Well, I've just about gotten to the point where I no longer have the slightest what's going on with this latest high end vid refresh. I mean, ATI and NVIDIA have really only recently been shipping the current generation of high end chips in anything approaching volume so the idea that new stuff is just around the corner really doesnt compute (not that it might not be true). Plus there's hardly any games that are worth playing much less need an even more powerful card (Doom3 = kack, HL2 pretty good but play it once and you've had enough), so where's the pressure to launch new stuff?


PLUS: I;ve had more than one source who normally know what they are talking about state that R520 is 16 pipes and not hugely hugely faster than R420. PLUS: I've seen an internal ATI document that seemed to state that R520 is 16 pipes (and R580, though that did seem to be fatter pipes - more texture units) (hard to explain how it "seemed" to state that, but without posting the document its hard to explain). And yet the weight of info that's beginning to come out makes me doubt everything. Oh, and I have heard from one source (an industry insider, but marketing not a tech guy, so it may be a case of a misunderstanding) that R520 is shader unified.

Conclusion: I am totaly flumoxed.

My info regards NV seems a little more straight foward - the next NV core will be NV40 with more quads, 6 quads i fact, but that is hardly rocket science to work out. My other info regards NV is that they do not have a schedule regarding the new part - that's not to say its not ready, but that the have not decided a roll out date.

I guess for ATI, they have been making hay with R300 fo so long now and they lack the PR checkbox called SM3, so they will jump first to be follwoed by NV.


I dont know, it seems to me things are going a bit nuts right now - all those "tweener" chips (R430, NV41 and 42), getting close to a new launch when the existing chip has hardly been a shipping product for more than a few months. And those totally ridiculous new notebook chips, it's getting out of hand. The pessimist in me thinks both NV and ATI are over stretching and that we are looking at another round of vaporware at launch anyway. I mean, both ATI and NV claimed at launch that X800 and GF6800 (respectively) were their best ramping, lowest fault development chips ever. What a load of absolute ballshite that turned out to be.

There, rant over!

[jbond04]

Does anyone else see a problem with the codename "Fudo"? Isn't that what everyone calls the Inq writer? The one who always comes here for rumors for his next article?

[caboosemoose]

Yeah, I still can't beleive that, he's such an F***wit. I reckon it's either not true or not quite what it seems somehow.

[Geo]

The "unified shader" thing could square the circle on the 16/24 conflicting info.

[caboosemoose]

The "unified shader" thing could square the circle on the 16/24 conflicting info.

Yes, that is true and its not the first time i ahve heard that expanation.

[kemosabe]

The "unified shader" thing could square the circle on the 16/24 conflicting info.

Well, according to the vibes Dave is emitting we are to expect neither more pipelines nor unified shaders from R520.

So the most uninspiring scenario would be just a tweaked shader architecture with FP32 and SM3.0 support on a spanking new silicon process. Perhaps a new AA algorithm? Performance boost 1.5X max.

*yawn*

[caboosemoose]

The "unified shader" thing could square the circle on the 16/24 conflicting info.

Well, according to the vibes Dave is emitting we are to expect neither more pipelines nor unified shaders from R520.

So the most uninspiring scenario would be just a tweaked shader architecture with FP32 and SM3.0 support on a spanking new silicon process. Perhaps a new AA algorithm? Performance boost 1.5X max.

*yawn*

Agreed and that is what all my own info says, but there does seem to be some momentum behind R520 being a bit more than that. I remember when R420 was launched and some NV employees I spoke were convinced that it was going to be 8 extreme pipes and apparently ATI had been circulated engineering samples with quads disabled leading some people to believe that it was indeed 8 pipes.

[Farid]

Sorry, but why would a different architecture preclude an increase in the number of pipes? NVDA changed their architecture from NV30 to NV40 and quadrupled the pipelines. I don't see any necessary relation.
Some people hinted that the R520 may share some technology from the Xbox 2 XeGPU (Unified architecture and rumored to have 8 pipelines).

I, therefore, suggested that maybe this "extreme pipeline" BS means they're using more ALUs per pipe, if so then I don't see the need of having 24 of them... Since most games are not fillrate bound, and future games won't be fillrate bound neither if this 700MHz rumor is true.

[kemosabe]

It might be a bit more than that, though I'm still having trouble reconciling how NVDA is allegedly going to tack on two more quads on a 0.11 or 0.13 process while R520 will supposedly still be limited to 16 pipes despite a large increase in transistor count and migration to 0.09u low-k (unless the core clock really gets to the 700MHz range). Something just doesn't seem to compute there.

[Geo]

The "unified shader" thing could square the circle on the 16/24 conflicting info.

Well, according to the vibes Dave is emitting we are to expect neither more pipelines nor unified shaders from R520.

So the most uninspiring scenario would be just a tweaked shader architecture with FP32 and SM3.0 support on a spanking new silicon process. Perhaps a new AA algorithm? Performance boost 1.5X max.

*yawn*

And in this scenario, how many transistors?

[egore]

I think ATI will have 3 versions of the R520, One with 16 pipes, 24 pipes and a limited edition 32 pipe card just for the sake of keeping the performance crown from Nvidia. A 32 pipe card will be memory bandwidth starved but it should still be fast enough to beat any refresh from Nvidia.

[kemosabe]

And in this scenario, how many transistors?

Search me.

I'm getting the feeling that they're trying to tell us that R520 will be much more of a "finesse" architecture than the brute force R420 approach. Stick to the 16 pipes at the high end; increase shader ALUs/efficiency, improve the memory controller, boost core clocks significantly thanks to 0.09u low-k and keep the transistor count reasonable to maximize yields and limit heat production. If they can get core clocks to 600MHz+, the mid-range 8 and 12-pipe parts could be extremely interesting. And ATI would be hoping to take back a significant lead in the mobile space where such an architecture would likely pay large dividends.

And NVDA responds in the high end with a 6-quad NV40 :?:

[tEd]

Must be a pain for those under NDA and watching this and similar threads but can't say anything :twisted:

[kemosabe]

They could at least indicate when we're on the right track, but no, that would be too congenial. :lol:

[caboosemoose]

Must be a pain for those under NDA and watching this and similar threads but can't say anything :twisted:

I don't think many people are under NDA - I don't know anyone who is under NDA on either chip. This time last year NVIDIA was briefing world and dog under NDA - I guess they were relieved to have a good part to push.

[tEd]

Must be a pain for those under NDA and watching this and similar threads but can't say anything :twisted:

I don't think many people are under NDA - I don't know anyone who is under NDA on either chip. This time last year NVIDIA was briefing world and dog under NDA - I guess they were relieved to have a good part to push.

I not necesseraily mean only press people. I think there are more people in the know who browse this forum than you might think.

[caboosemoose]

Must be a pain for those under NDA and watching this and similar threads but can't say anything :twisted:

I don't think many people are under NDA - I don't know anyone who is under NDA on either chip. This time last year NVIDIA was briefing world and dog under NDA - I guess they were relieved to have a good part to push.

I not necesseraily mean only press people. I think there are more people in the know who browse this forum than you might think.

Yeah, sure. But I still think they are both keeping their cards quite close to their chests right now.

[Geo]

And NVDA responds in the high end with a 6-quad NV40 :?:

A six-quad NV40 would kill the R520 you've described. Tho possibly we're mixing time frames --are you expecting 6-quads from 110nm?

[pakotlar]

look i heard that the r520 will actually have only 2 pipes, but they will be "extreme" pipes. if you know what i mean. nudge nudge, wink wink.

[kemosabe]

And NVDA responds in the high end with a 6-quad NV40 :?:

A six-quad NV40 would kill the R520 you've described. Tho possibly we're mixing time frames --are you expecting 6-quads from 110nm?

Personally, I just can't imagine a NV40 architecture with two additional quads on 0.11u. The die size and heat production would seem prohibitive. If they're not prepared to go to 0.09u yet, my guess is they're going to rely on a slightly faster NV40 and SLI until the fall.

[FlungDung]

And NVDA responds in the high end with a 6-quad NV40 :?:

A six-quad NV40 would kill the R520 you've described. Tho possibly we're mixing time frames --are you expecting 6-quads from 110nm?

Personally, I just can't imagine a NV40 architecture with two additional quads on 0.11u. The die size and heat production would seem prohibitive. If they're not prepared to go to 0.09u yet, my guess is they're going to rely on a slightly faster NV40 and SLI until the fall.


Can two quads be added to NV40 thru additional layers on the chip, hence limiting die size?

Or does chip design not work that way?

[pakotlar]

And NVDA responds in the high end with a 6-quad NV40 :?:

A six-quad NV40 would kill the R520 you've described. Tho possibly we're mixing time frames --are you expecting 6-quads from 110nm?

Personally, I just can't imagine a NV40 architecture with two additional quads on 0.11u. The die size and heat production would seem prohibitive. If they're not prepared to go to 0.09u yet, my guess is they're going to rely on a slightly faster NV40 and SLI until the fall.


Can two quads be added to NV40 thru additional layers on the chip, hence limiting die size?

Or does chip design not work that way?

If you make the die smaller you increase the chip's thermal density.

[Megadrive1988]

According to the article the ATi SLI won't be limited to 2 cards. I just have to wonder if there will be some crazy Alienware box with 4 of these babies in it. Now that would be certifiably insane :shock:
Just one of these would be quite nice though... no I think it would be very nice actually :) I guess we'll see how things shape up pretty soon but I know a lot of people here have been saying that there is no way we'll see a 2x speed jump in this next generation. It would be nice to see them proven wrong (I doubt they'll mind :wink: ).

mini RenderBeast! :shock: 8)

[Megadrive1988]

my reasonable expectations slash guesses:

*1.5 times aka 50% faster than Radeon X850 in general situations, as far as pixel fillrate performance. going from 16 pipelines to 24 pipelines

*modest increase in geometry / vertex shader performance. going from 6 vertex shaders to 8.

*Shader Model 3.0+
(whereas the more advanced Xenon GPU will be SM3.0++ or SM3.5)

*not* a unified shader architecture, or at least not completely unified

*in some situations, we might see 2x the performance in pixel shader heavy applications, due to more ALUs per pipeline, or better ALUs or whatever.

*Ati Multi Rendering, MVP or whatever. 2 cards (not 4) for consumer/gamer use

[Megadrive1988]

Dave is that more reasonable ?

[tEd]

Just think it will be x850xtpe performance with SM3 so at least you won't get disappointed :P

[JD]

I'm not interested in ati hw unless they surpass nv gl driver. I do like their hw and lower prices on it but the drivers, ugh...

[Moloch]

Just think it will be x850xtpe performance with SM3 so at least you won't get disappointed :P
I hope they atleast improve stencil shadow performance.

[Ailuros]

*Shader Model 3.0+
(whereas the more advanced Xenon GPU will be SM3.0++ or SM3.5)

Someone correct me if I'm wrong but this far WGF2.0 mentions only Shaders AFAIK (w/o a version number).

I still don't get what this +, ++ stuff is supposed to mean anyway. An architecture can be nowadays either WGF1.0 (DX9.0) or in the future WGF2.0 compliant.

Xenon might have unified units, but I don't think it'll be WGF2.0; the Geometry shader isn't optional from what I recall. So it's either/or and both the console as the upcoming PC chip will be SM3.0 compliant chips and that's it.

NV40 claims already unlimited shader calls (in relative terms; well it's in relative terms too in WGF2.0).

MaxPS30 instruction slots = 4096
MaxVS30 instruction slots = 544

Some driver indications exposed for ATI's upcoming VPU (no idea if that stuff is accurate or not):

MaxPS30 instruction slots = 512
MaxVS30 instruction slots = 1024

In any case that stuff isn't that important, what's important is what comes out at the other end and not what anyone might claim on paper.

-------------------------------------

R520 as NV-"whatever" with fillrates close to or higher than 10GPixels/sec will really set off IMHO, when GDDR4 (thanks XMas ;) ) will become available towards the end of the year. Until then any performance increase in analogy to the increased fillrate will be restricted to those cases where bandwidth doesn't really matter. Are you speculating XZ% for an average across the board increase or as a best case scenario where you'd be better off using up to....?

[Ailuros]

By the way....

*modest increase in geometry / vertex shader performance. going from 6 vertex shaders to 8.

Why would the increase here be "modest" and in other cases not? In a specialized synthetic application that measures geometry throughput, I'd say that the increase between let's say 540*6 and hypothetically =/>650*8 will be anything but modest.

[Dave Baumann]

I think what people need to bear in mind is that even with non-unified structures the "pipeline" doesn't really tell us much about performance. Current high end boards have "16 pipelines", but realistically there are very few scenarios where you be getting 16 (or 32 in some of NV40's cases) "outputs per clock", witness the arrangement of NV43's fragment to ROP pipelines. Should “hypothetical new architecture x” have fewer pipelines than “hypothetical refresh y” that doesn’t really give any indication of the composition of the structure of pipelines of x - how many instructions per clock, its per quad efficiency, overall architectural efficiency, ROP output capabilities, etc., etc., hence its relative performance against y. In many respects the newer parts are more likely going to be about making sure the ROP's are kept busier by various methods.

Should NVIDIA be going to “24 pipelines” then they are probably doing so because the architectural layout of their pipelines is already fairly set in stone for this cycle and their overall pipeline composition probably won’t change massively significantly. The big unknown is what is R520’s pipeline composition and (what really matters) how good is that composition going to be in games.

While I may have an inkling about the top line specifications I presently have no clue about the composition underneath them, and even then I couldn’t necessarily state (although I could have a guess) without seeing the performance whether that translates into good or bad game performance. For instance, where the shader architecture is concerned what will R520’s ALU composition be? Will it still be the same as R300 but extended for FP32 and SM3.0 instructions, will they have done something like beefed up the second ALU with a more compete instruction set or will they have done something very different? Who knows at this point, all I can say is that when I tried to tease some information a while back I was slightly ominously, for ATI, reminded that R520 was primarily designed when ATI had a huge shader advantage with R300 vs NV30…

[digitalwanderer]

all I can say is that when I tried to tease some information a while back I was slightly ominously, for ATI, reminded that R520 was primarily designed when ATI had a huge shader advantage with R300 vs NV30…
Very interesting tiddy-bit, thanks Dave. :)

[trinibwoy]

Who knows at this point, all I can say is that when I tried to tease some information a while back I was slightly ominously, for ATI, reminded that R520 was primarily designed when ATI had a huge shader advantage with R300 vs NV30…

i.e, ATI underestimated with Nvidia would do with NV40 and aimed lower?

[WaltC]

Also, whenever I hear the term "extrememe pipelines" now or any variation on that theme I just have this humongoid bullshit alarm that goes off.... http://66.224.5.66/board/images/smilies/bleh2.gif

Agreed about that, but in this case it may simply mean that they've increased the throughput performance of each pipeline by 30% per clock over the per-clock pipeline performance of R4x0, or something along those lines (may have something to do with bandwidth improvements, etc.)

Or it may just be cleverly deposited misinformation dropped here and there to mislead competitors into thinking "ATi's going 24 pixels per clock" when they really plan to do 32...;)

[Geo]

Should “hypothetical new architecture x” have fewer pipelines than “hypothetical refresh y” that doesn’t really give any indication of the composition of the structure of pipelines of x - how many instructions per clock, its per quad efficiency, overall architectural efficiency, ROP output capabilities, etc., etc., hence its relative performance against y.

I get this. What I was obliquely objecting to upstream is a train of thought that suggests ATI stands pat on number of pipelines *and* (largely, at least, with only minor tweaks) on the organization/composition of same. I just don't see *both* happening, particularly in a major process move.

[WaltC]

...
While I may have an inkling about the top line specifications I presently have no clue about the composition underneath them, and even then I couldn’t necessarily state (although I could have a guess) without seeing the performance whether that translates into good or bad game performance. For instance, where the shader architecture is concerned what will R520’s ALU composition be? Will it still be the same as R300 but extended for FP32 and SM3.0 instructions, will they have done something like beefed up the second ALU with a more compete instruction set or will they have done something very different? Who knows at this point, all I can say is that when I tried to tease some information a while back I was slightly ominously, for ATI, reminded that R520 was primarily designed when ATI had a huge shader advantage with R300 vs NV30…

But if we harken back to the days of nV3x I recall all kinds of strange and bizarre emphasis being put on ROPs, ALUs, and compilers for nV3x--none of which made the slightest bit of difference in the fact that R3x0 roasted nV3x alive in every category that had meaning inside the games developers had written then (and the ones they've written since)...;)

I think you have it right, though, in that what will matter is the kind of performance developers are able to harness in their games from any new architecture. Another way to interpret what you were told about the R3x0 vs. nV3x shader gap might be: "Remember the R3x0-nV3x shader gap? We want to do it again with R5x0"...;) I guess it would depend on whether the R5x0 info you reference here was provided before or after nV4x had shipped. If before, then I'd imagine your interpretation might well be correct--however, the info would also be very dated and may not currently be applicable. If after, then it might well be along the lines of what I've suggested. I mean, one very good reason I can see for ATi not jumping orgasmically onto the "SLI" doublemint-twins experience might be because they know that what they've got coming up might obsolete it in practical terms overnight. Guess we'll have to wait a few months to see...

If they anounce it in June we can only hope they'll ship it by Christmas...:D

[Geo]

Who knows at this point, all I can say is that when I tried to tease some information a while back I was slightly ominously, for ATI, reminded that R520 was primarily designed when ATI had a huge shader advantage with R300 vs NV30…

i.e, ATI underestimated with Nvidia would do with NV40 and aimed lower?

Gosh, graphics card designers are worse than Generals, who are famous for always fighting the last war. . .which is one war more recently than graphics card designers, apparently. .. .

[digitalwanderer]

Dumb question, but how much info does nVidia have on the R520 or are they playing the same guessing games we are right now?

Also someone like Asus, who makes cards by both....do they have a bit more insite or are they as blind/dumb as we are until ATi makes the announcement official? :|

[tEd]

Dumb question, but how much info does nVidia have on the R520 or are they playing the same guessing games we are right now?

Also someone like Asus, who makes cards by both....do they have a bit more insite or are they as blind/dumb as we are until ATi makes the announcement official? :|

you may ask DP

[digitalwanderer]

you may ask DP
Well, not without violating a court order or two.

Stupid restraining orders... :oops:

[tEd]

you may ask DP
Well, not without violating a court order or two.

Stupid restraining orders... :oops:

8)

[Geo]

The nv30 comparison occurred to me too. I was remembering Kirk in run-up days opining that performance qua performance had nearly peaked in useful terms and we should be much more interested in better looking pixels.

Thing is, that which was ridiculous to attempt with 4 pipes and a 128-bit bus may not be so ridiculous with 16 pipes and a 256-bit bus. Not that I would suggest "NV30 done *right*!" as a marketing slogan for ATI. . .

I wouldn't mind seeing a generic, lasting bump up in IQ settings driven all the way thru the mainstream where it becomes pointless to run a game or benchmark an app with those settings turned off. I'm not sure what that means --single cycle 4xaa/4xaf? I dunno.

[trinibwoy]

Another way to interpret what you were told about the R3x0 vs. nV3x shader gap might be: "Remember the R3x0-nV3x shader gap? We want to do it again with R5x0"...;)

I don't see how this interpretation is feasible. Wasn't R520 designed long before NV40 saw the light of day? If NV3x was their baseline for comparison they would've had a pretty f'ed up baseline to work with.

[WaltC]

Dumb question, but how much info does nVidia have on the R520 or are they playing the same guessing games we are right now?

Also someone like Asus, who makes cards by both....do they have a bit more insite or are they as blind/dumb as we are until ATi makes the announcement official? :|

I think that both companies use all of their sources of indirect and anecdotal information to form a picture of where they think the other guy will go. Sometimes both companies may have agreements or arrangements with the same third-party companies (such as board OEMs) and in those relationships are able to piece together guesstimates as to the direction their competitors will take. Then there's the fact that they share FABs and so each company is served by the same information there as to what can be made and what can't be--what is likely and what isn't--etc. (I won't bother saying anything about espionage--which is always a possibility...;))

NDAs are often effective in terms of public disclosure and theoretically should serve similarly in private transactions among companies operating in a triangle relationship--but private breaches of NDA are much harder to prove since generally such breaches by nature are never revealed publicly. If you don't know something has been revealed you cannot very well object to it, etc., let alone prove it..;)

nV and ATi split off into two separate directions in 2002 with nV3x and R3x0, respectively. As we know, ATi took the more profitable and advantageous path with R3x0 and so nV abandoned its V3x strategies (stubbornly and ungraciously to be sure), but to its credit nV eventually recognized nV3x for the competitive dead-end that it was. With nV4x, nV jumped whole hog onto the R3x0 paradigm of things to come.

So now we don't have, it seems to me, a situation where each company is taking its own divurgent path anymore, and as nV is effectively following ATi at the moment and attempting to one-up them at their own game I think ATi definitely has its work cut out for it. But being "the leader" is always more difficult than following, so this isn't surprising.

nV's chief mistake with nV3x was that the company was premature in assuming its leadership role in the 3d gpu business when in fact it had become basically a "sitting duck" for a company like ATi to target--success often makes technology companies like nV (or Intel, for that matter) lazy and they become prime targets for competitors. Now that the shoe is on the other foot it remains to be seen whether ATi will fare better over the long run.

I think the signs are encouraging, though, that ATi is not ready to get lazy and slothful just yet. The Catalyst driver program, for instance, is I think the best I've ever seen from a 3d-card OEM. Although nV's had plenty of time to counter it doesn't seem as if the company is yet within striking distance of the Catalyst program (at least, enough to influence me in nV's direction.) Anyway, I think that by the end of the year we'll know whether ATi will retain a firm grip on what it's accomplished or whether a few things will slip through its fingers. It's difficult to retain the degree of focus necessary to stay out in front and the tendency is to let things slide and open some windows to your competitors.

One last encouraging sign from ATi that it understands that "leadership" means that you don't incessantly copy the other guy, is that ATi has been very slow to jump on the doublemint-SLI bandwagon. I'm hoping that they never do, but that's just me. I'd be disappointed if ATi were to mimic every little thing nV announces or does because leaders don't behave in that fashion. I would, however, like to see ATi come up with something better and much more practical than nVidia's current approach, and here's hoping that the delay in announcing a copy-cat product is occurring exactly for that reason. Should be an interesting year...;)

[WaltC]

I don't see how this interpretation is feasible. Wasn't R520 designed long before NV40 saw the light of day? If NV3x was their baseline for comparison they would've had a pretty f'ed up baseline to work with.

I would venture to say that even at this late date there are still some things being hammered out and finalized relative to the R520 design. Don't mistake when design of an architecture begins with when it ends, is all I can say...;)

[kemosabe]

Another way to interpret what you were told about the R3x0 vs. nV3x shader gap might be: "Remember the R3x0-nV3x shader gap? We want to do it again with R5x0"...;)

I don't see how this interpretation is feasible. Wasn't R520 designed long before NV40 saw the light of day? If NV3x was their baseline for comparison they would've had a pretty f'ed up baseline to work with.

Well considering that NV40 reviews started cropping up way back in April 2004, and that R520 allegedly taped out only a few months ago, you'd think ATI would have had ample time to make any necessary adjustments to the design before sending it off to TSMC. It would just seem slightly ridiculous for ATI to be "stuck" with a suboptimal R520 pipeline architecture that was set in stone from even before R420 was released.

Dave's cryptic hints sometimes suggest that he is supremely confident about knowing what ATI has in store, and now he's essentially conceded to having significant gaps in his info. Seems to me like we're back to square one and know nothing concrete.

[Geo]

nV and ATi split off into two separate directions in 2002 with nV3x and R3x0, respectively. As we know, ATi took the more profitable and advantageous path with R3x0 and so nV abandoned its V3x strategies (stubbornly and ungraciously to be sure), but to its credit nV eventually recognized nV3x for the competitive dead-end that it was. With nV4x, nV jumped whole hog onto the R3x0 paradigm of things to come.

So now we don't have, it seems to me, a situation where each company is taking its own divurgent path anymore, and as nV is effectively following ATi at the moment and attempting to one-up them at their own game I think ATi definitely has its work cut out for it. But being "the leader" is always more difficult than following, so this isn't surprising.


Yes, but will this still look true in another two months? If ATI is going to 90nm without a significant (or any) increase in pipes, then Something is Going On at a pretty fundamental level to shake up the pieces on the board.

[kemosabe]

It would certainly seem that way. Unless ATI has in effect come to the conclusion (as some have argued) that significantly improving its shader architecture will have far more impact on performance than increasing the pipeline count. Which is why I have difficulty imagining that neither one nor the other of these enhancements will find its way into R520. If they're going to be charging over $600 for these new cards, they sure as hell can't expect not to provide better game performance and image quality. :?

[wireframe]

If they're going to be charging over $600 for these new cards, they sure as hell can't expect not to provide better game performance and image quality. :?

With memory sizes set to make the jump from 256MB to 512MB, the pricing issue may very well be justified that way.

[Geo]

Let's try this thought experiment:

You have three architectures, A, B, and C. A is where you are now. C is where you feel pretty strongly (at least in its high-level details) you need to be about 12-18 months after B appears. C is also, in your judgement, the major market inflection point for a few years on either side of it. A and C look a whole lot different than each other. Unfortunately, the API and OS support for C isn't finalized and won't be available until much closer (or even a little after --see R300) C appears.

Mightn't you decide to make B look a lot more like C than A, without going the whole hog? Not quite enough to claim it is actually C, but enough to try out major elements of the low-level infrastructure in the real world, get that feedback, and tweak/perfect for when you introduce C to the world?

Or do you end up with a bloody mess that doesn't do anything well? :?

[Farid]

Should “hypothetical new architecture x” have fewer pipelines than “hypothetical refresh y” that doesn’t really give any indication of the composition of the structure of pipelines of x - how many instructions per clock, its per quad efficiency, overall architectural efficiency, ROP output capabilities, etc., etc., hence its relative performance against y. In many respects the newer parts are more likely going to be about making sure the ROP's are kept busier by various methods.
In english, I think that means that Dave thinks Ati won't go the "more pipelines" route, but go the same or fewer # of pipes but more capable.

Actually, that would be my bet too.

[hovz]

...
While I may have an inkling about the top line specifications I presently have no clue about the composition underneath them, and even then I couldn’t necessarily state (although I could have a guess) without seeing the performance whether that translates into good or bad game performance. For instance, where the shader architecture is concerned what will R520’s ALU composition be? Will it still be the same as R300 but extended for FP32 and SM3.0 instructions, will they have done something like beefed up the second ALU with a more compete instruction set or will they have done something very different? Who knows at this point, all I can say is that when I tried to tease some information a while back I was slightly ominously, for ATI, reminded that R520 was primarily designed when ATI had a huge shader advantage with R300 vs NV30…

But if we harken back to the days of nV3x I recall all kinds of strange and bizarre emphasis being put on ROPs, ALUs, and compilers for nV3x--none of which made the slightest bit of difference in the fact that R3x0 roasted nV3x alive in every category that had meaning inside the games developers had written then (and the ones they've written since)...;)

I think you have it right, though, in that what will matter is the kind of performance developers are able to harness in their games from any new architecture. Another way to interpret what you were told about the R3x0 vs. nV3x shader gap might be: "Remember the R3x0-nV3x shader gap? We want to do it again with R5x0"...;) I guess it would depend on whether the R5x0 info you reference here was provided before or after nV4x had shipped. If before, then I'd imagine your interpretation might well be correct--however, the info would also be very dated and may not currently be applicable. If after, then it might well be along the lines of what I've suggested. I mean, one very good reason I can see for ATi not jumping orgasmically onto the "SLI" doublemint-twins experience might be because they know that what they've got coming up might obsolete it in practical terms overnight. Guess we'll have to wait a few months to see...

If they anounce it in June we can only hope they'll ship it by Christmas...:D

i dotn see how it can be taken any other way then him hinting at the r520 being a letdown. for it to be taken any other way would only mean dave/the source of that comment isnt that familiar with english.

[kemosabe]

In english, I think that means that Dave thinks Ati won't go the "more pipelines" route, but go the same or fewer # of pipes but more capable.

Actually, that would be my bet too.

Just a thought, but then it might boil down to finding an equilibrium point and offering some other tangible benefits to the consumer in exchange. Assuming that more capable pipelines and higher clocks can get you a 30-50% FPS increase at max settings in most modern shader-intensive games (+/- any improvements in image quality), then it would make sense if this allowed for a relatively smaller die size on the 0.09u process and hence higher yields, lower production costs and a lower price on the shelf. This would run against the current trend of ballooning prices in the high end, and could contribute to changing market dynamics (further increasing the demand for higher-margin flagship cards, including the mobile versions). Somehow with TSMC's early ramp costs on 0.09u and the jump to 512MB GDDR3 memory, I don't believe the proper ingredients are available yet for this recipe to be successful. Perhaps ATI think/know otherwise.

[ninelven]

I don't believe the proper ingredients are available yet for this recipe to be successful. Well, I'd say we've entered the shader heavy era, and that it is quite logical at this time and going forward.

[Headstone]

Would it be possible that they would increase the number of vertex shaders from 6 to 8 and keep the pipelines at 16? Hence the supposed 24 pipes. Then increasing the core clock to over 600 and having the memory run in excess of 1500MHz and beefing up the ALUs?

[Geo]

Would it be possible that they would increase the number of vertex shaders from 6 to 8 and keep the pipelines at 16? Hence the supposed 24 pipes. Then increasing the core clock to over 600 and having the memory run in excess of 1500MHz and beefing up the ALUs?

Well, that's the 64k question, isn't it? Unless you pour an awful lot of content into "beefing up the ALUs" that includes some "& etc" and "a bit of this and that" you probably can't get to the number of transistors that 90nm should be able to give you for a high-end part. But then maybe they won't push 90nm to the max with Mark 1 and leave some in the bank? But if they don't, can they count on NV not to? It would run counter to most of what I think we know of the history of the industry over the last 10 years, and particularly the last five.

[ANova]

Would it be possible that they would increase the number of vertex shaders from 6 to 8 and keep the pipelines at 16? Hence the supposed 24 pipes. Then increasing the core clock to over 600 and having the memory run in excess of 1500MHz and beefing up the ALUs?

That would be my guess.

[Pete]

Or ATi may have separated the ROPS from the pipes, as nV did. I wonder which is easier for them to do, coming from R300: more pipes and fewer ROPs, or ROPs still inline with higher IPC pipes? I would infer the former, considering Dave's "ominous" ATi statement. I'm guessing the more radical changes will arrive with R500/600.

Another way to interpret what you were told about the R3x0 vs. nV3x shader gap might be: "Remember the R3x0-nV3x shader gap? We want to do it again with R5x0"...Walt, those glasses aren't rose-tinted, they're just made of roses.

[Chalnoth]

Or ATi may have separated the ROPS from the pipes, as nV did. I wonder which is easier for them to do, coming from R300: more pipes and fewer ROPs, or ROPs still inline with higher IPC pipes? I would infer the former, considering Dave's "ominous" ATi statement. I'm guessing the more radical changes will arrive with R500/600.
Well, fewer ROPs with more pipelines is going to be more efficient (i.e. higher performance fo the same number of transistors), for the simple reason that it's always more challenging to increase IPC than increase parallelism.

[Pete]

Interestingly enough, nV basically did both with NV40. So it's not impossible for ATi to do the same, given how long they've had to work on a post-R300 architecture (one year/generation more than nV, if R520 launches in May/June).

Am I right in thinking that separating the ROP from the rest of the pixel pipeline (via crossbar switch or FIFO) is more of an engineering task, whereas gearing for higher IPC is more of an architectural/management task? Obviously you need engies for both, but the former seems like it can be undertaken (loosely speaking) without regard to shader voodoo, whereas that voodoo gets to the core of, well, the new core.

So maybe it's more likely that R520 (and beyond) will separate ROPs from pipes, whereas it's harder to see if ATi will "just" increase the pipes rather than more thoroughly rework them.

Although adding the FP buffers and offering the longer shaders of NV40's SM3"+" doesn't sound like a cakewalk, either.

[Ailuros]

Given the estimated timing of R520's tapeout, I doubt ATI had enough time for any significant changes after the NV40 introduction. I would even guess that ATI had already sent back then the chip to the fab.

Then increasing the core clock to over 600 and having the memory run in excess of 1500MHz and beefing up the ALUs?

Probably yes to all 3, with the only other difference that I doubt that higher speced ram will be available before fall this year. That would mean that whatever ATI/NV have planned for this spring it will have to get along with GDDR3 and refreshes later on will get the bandwidth they'd theoretically need to feed the underlying fill-rate.

I've no idea what exactly ATI or NVIDIA have done with their upcoming architecture, but either way I'd say that 16 ROPs are more than enough for the foreseeable future, whereby of course the same "rule" - as Dave already noted - applies: ROP =! ROP necessarily, especially between two architectures.

At least for NVIDIA I'd figure that NV43 is a quite safe baseline to speculate on for upcoming releases.

***edit: I think most of us would like to see significant performance increases from either/or this year. Any new release with let's say a 20-30% performance increase across the board compared to current boards is going to be more than just boring. The more the merrier....

[Ailuros]

Pete,

So maybe it's more likely that R520 (and beyond) will separate ROPs from pipes, whereas it's harder to see if ATi will "just" increase the pipes rather than more thoroughly rework them.

One reason to increase the number of quads is that increasing the clockspeed significantly on a given manufacturing process is a no-go.

ATI/R520 isn't facing such a problem, since they jumped on the 90nm bandwagon first. On the other hand if NVIDIA has planned a spring refresh to counter R520 and since from what it looks like they won't be able to have a 90nm product prior to fall this year, the only other reasonable chance IMHO to reach a specific fill-rate is to increase the amount of quads on whatever else process is available to them.

I can theoretically reach 9.6GPixels/sec either with 4 quads@600MHz or alternatively with 6 quads@400MHz (oversimplyfied example).

[Chalnoth]

90nm won't necessarily translate to higher clockspeeds. Witness the Athlon 64 90nm designs.

[Unknown Soldier]

well let's do some maths

16pipes * 1.3 = 20.8 .. so it can't be this
24pipes * 1.3 = 31.2 .. close to 32

Hmm..

US

[chavvdarrr]

90nm won't necessarily translate to higher clockspeeds. Witness the Athlon 64 90nm designs.
you mean P4? :)

[_xxx_]

Can two quads be added to NV40 thru additional layers on the chip, hence limiting die size?

Or does chip design not work that way?

No.

[_xxx_]

well let's do some maths

16pipes * 1.3 = 20.8 .. so it can't be this
24pipes * 1.3 = 31.2 .. close to 32

Hmm..

US

Bad logic IMHO. What's that "1.3" bull all about anyway?

[Unknown Soldier]

So this time we'll get the EXTREME pipes then. :)
24x1.3=oh baby!

I dunno folks, i think it sounds a little too good to be true. But i'm gonna be the first in line to buy one anyway. I'll be happy if it's faster than a 600/595 MHz X800 XT PE. :lol:

This sounds great, we have the obligatory "several insider sources", we have the, now classic, "Extreme pieplines" and we have the "twice faster than previously released X card". We definitely have a lot of the right ingredients for one of thoses, always ressourceful, 20 pages BS speculations thread.

Now, this thread lacks some essential elements, such as the "Ati has something big up their sleeve, can't say anymore" card, we also need some insider tidbits provided by someone who act like he's in the know, but he, in reality, is full of it. And only then, we'd be able to consider this thread a "good one".

Never mind me, I'm just kidding, but, seriously, 1.3 pipelines? Laughing

]We have confirmed the 24 pipelines rumors from several independant sources. However, these 24 pipelines are not comparable to 24 of today's pipelines - multiply by 1.3. So the 24 pipelines will have the performance of 32 "normal" pipelines.

Ye .. I know it's bad logic

[Jawed]

90nm won't necessarily translate to higher clockspeeds. Witness the Athlon 64 90nm designs.

When I made that point many moons ago, Baumann said "no".

Jawed

[PatrickL]

My concern is a bit different. It seems that people are reporting that all ATI next gen chips will be on 0.09. But ATI will not be alone using that process so I wonder how that will be possible to have so many chips on that process without being held back with fabs production constraints ?

[Ailuros]

90nm won't necessarily translate to higher clockspeeds. Witness the Athlon 64 90nm designs.

ATI's yield from what I keep hearing is quite a bit beyond 600MHz. Try to replicate such a clockspeed with 130nm with the estimated board complexity.

R480 is already at 540MHz@low-k 130nm.

Besides why on God's green earth would I compare a CPU with a GPU? The lowest Athlon64 runs at about 5x times the frequency of a NV40.

[kemosabe]

My concern is a bit different. It seems that people are reporting that all ATI next gen chips will be on 0.09. But ATI will not be alone using that process so I wonder how that will be possible to have so many chips on that process without being held back with fabs production constraints ?

There have been suggestions that 0.09u capacity at TSMC will be plentiful, at least far in excess of what they had at 0.13u low-k. One report even had TSMC actively seeking out new customers to fill that capacity.

[Sunrise]

90nm won't necessarily translate to higher clockspeeds. Witness the Athlon 64 90nm designs.

ATI's yield from what I keep hearing is quite a bit beyond 600MHz. Try to replicate such a clockspeed with 130nm with the estimated board complexity.

R480 is already at 540MHz@low-k 130nm.

Besides why on God's green earth would I compare a CPU with a GPU? The lowest Athlon64 runs at about 5x times the frequency of a NV40.

AiL, R480 is @ 540Mhz, yes.

Problem is, R480 is their (don´t even count re-spins) 2nd revision of that chip, since R420 wasn´t really that "easy" to produce in sufficient quantity. (according to a conference call). However, from what i´ve been hearing, 90nm Low-K "Nexsys" seems to be quite successful at this stage, capacity is a lot higher, so maybe this shouldn´t be a problem anymore.

I would say about 550MHz with 24 pipes is feasible, while each pipe should have at least x1.3 the performance of one R480-pipe. R580 should then be to R520 what R480 was to R420.

[Pete]

A higher-yield respin? That would put "quite successful" into further uninspiring context. :)

[Headstone]

6x1.3=8

or at least 7.8 but that would explain the 1.3 number in the increase in vertex shaders

[MuFu]

Nobody thinks 16p/8v@650-700MHz with a big per-clock efficiency improvement? Keeping the ALUs busy will have received a massive design push since the day they started working on a unified architecture.

I've heard 16@650MHz, but in the weeks running up to the R420 launch the word was of a 12-pipe part. So who knows...

[tEd]

Nobody thinks 16p/8v@650-700MHz with a big per-clock efficiency improvement? Keeping the ALUs busy will have been a major design push since the day they started working on a unified architecture.

I've heard 16@650MHz, but in the weeks running up to the R420 launch the word was of a 12-pipe part. So who knows...

Actually i have thought through every possible scenario but it doesn't help satisfie me because it's all speculation :wink:

[MuFu]

True, true.

[Geo]

Nobody thinks 16p/8v@650-700MHz with a big per-clock efficiency improvement? Keeping the ALUs busy will have been a major design push since the day they started working on a unified architecture.

I've heard 16@650MHz, but in the weeks running up to the R420 launch the word was of a 12-pipe part. So who knows...

Actually i have thought through every possible scenario but it doesn't help satisfie me because it's all speculation :wink:

This is my favorite time of year right up to about two weeks after launch. :D Just need a legit tidbit or two once in awhile to keep it perking along.

[digitalwanderer]

Actually i have thought through every possible scenario but it doesn't help satisfie me because it's all speculation :wink:
Ah, but speculation in and of itself is kind of the end-goal for me....so it's all good. 8)

Jeeze, if I really wanted to know that badly I think I'd just ask someone; but then I wouldn't get to play guess-along with everyone else anymore. :?

That ain't no fun. I tried it once, didn't like it....since then I've avoided knowing many NDA type things prefering to have the liberty/freedom to figure them out. 8)

[tEd]

Actually i have thought through every possible scenario but it doesn't help satisfie me because it's all speculation :wink:
Ah, but speculation in and of itself is kind of the end-goal for me....so it's all good. 8)



Then you must be in a very high excitement state every day for the last couple of months.

I'm kinda jealous :lol:

[digitalwanderer]

Then you must be in a very high excitement state every day for the last couple of months.
You ever lean back in your chair really far to just about as far back as you can balance yourself without falling over backwards? Then you lean back just a little bit more and start to go over backwards but with a jerk of your body recover your balance just before falling over? You know how you feel when that little jerk hits?

I feel that way all the time. 8)

[kemosabe]

Nobody thinks 16p/8v@650-700MHz with a big per-clock efficiency improvement?

Seems to me that's been the more popular theory over the last couple of pages, n'est-ce pas?

But then I'd expected you or Dave to toss another grenade into the speculation and run away. :lol:
Is it safe to say that we (almost) have a level playing field this time around?

[Geo]

Nobody thinks 16p/8v@650-700MHz with a big per-clock efficiency improvement?

Seems to me that's been the more popular theory over the last couple of pages, n'est-ce pas?

But then I'd expected you or Dave to toss another grenade into the speculation and run away. :lol:
Is it safe to say that we (almost) have a level playing field this time around?

Somewhere's around here I quoted Damon Runyan to the effect that the smart money, ignoring all rumors, is still going with a 24-pipe part rather than the perceived risk of serious mucking about with the architecture this time around. Unstated (mostly) support for this position is the specter of the con-job ATI did last time with specs in lead-up days. I believe our gracious host was fed (whether it was directly, or indirectly thru partners, I'm not sure) that line o' bull last time, and might be being fed misinformation again --tho how much he actually believed, this time or last, only he can say.

But then conventional wisdom is wrong often enough to make this kind of thing fun and not-entirely pointless. :lol:

Not sure how you jumped to "level playing field" tho; you left me in the dust on the transition. . .

[Geo]

Then you must be in a very high excitement state every day for the last couple of months.
You ever lean back in your chair really far to just about as far back as you can balance yourself without falling over backwards? Then you lean back just a little bit more and start to go over backwards but with a jerk of your body recover your balance just before falling over? You know how you feel when that little jerk hits?

I feel that way all the time. 8)

So otherwords you're an adrenaline-junkie? :D

[kemosabe]

Not sure how you jumped to "level playing field" tho; you left me in the dust on the transition. . .

No, I wasn't referring to a level playing field between ATI and NVDA. I meant that neither MuFu nor Dave seemed all too sure of themselves with respect to what ATI has done with R520, which is not the impression I've had in previous generations. One or both of them will surely get tipped before the rest of us, but for now it looks like we're pretty much in the same boat.

[digitalwanderer]

So otherwords you're an adrenaline-junkie? :D
Nope, adrenaline-junkies seek it out....with me it just happens. :oops:

[Geo]

Not sure how you jumped to "level playing field" tho; you left me in the dust on the transition. . .

No, I wasn't referring to a level playing field between ATI and NVDA. I meant that neither MuFu nor Dave seemed all too sure of themselves with respect to what ATI has done with R520, which is not the impression I've had in previous generations. One or both of them will surely get tipped before the rest of us, but for now it looks like we're pretty much in the same boat.

Ah! Thanks. Part of their caution might be that they know they got burned last time and wondering if they're being set-up again (speculation on my part). Which is a whole different discussion: if ATI keeps doing that kind of thing when will it start to have consequences on their relationships with partners, high-profile webmasters, etc?

[digitalwanderer]

if ATI keeps doing that kind of thing when will it start to have consequences on their relationships with partners, high-profile webmasters, etc?
When they quit wanting insider-info to lord over us, ie never. ;)

Need an example? Take a look at nVidia, they have happily shovelled sooo much BS to partners/webmasters but they still gots people lining up to feed at their trough.

[Geo]

if ATI keeps doing that kind of thing when will it start to have consequences on their relationships with partners, high-profile webmasters, etc?
When they quit wanting insider-info to lord over us, ie never. ;)

Need an example? Take a look at nVidia, they have happily shovelled sooo much BS to partners/webmasters but they still gots people lining up to feed at their trough.

I think you're pointing at extreme Consequences of the "never let your shadow cross my path again!" variety. There are consequences short of that --and NV got a pretty good taste of that for a couple years there.

[digitalwanderer]

I think you're pointing at extreme Consequences of the "never let your shadow cross my path again!" variety. There are consequences short of that --and NV got a pretty good taste of that for a couple years there.
Pffft! They walked and were more than gladly helped to walk away from that fiasco of theirs, very few held/hold them accountable.

I'm still disgusted over a number of places and how they dealt/deal with that. :?

[Farid]

Pffft! They walked and were more than gladly helped to walk away from that fiasco of theirs, very few held/hold them accountable.
What did you expect? Torches, pitchfork, angry mobs, tar and feathers?
We already have internet forums for this kind of stuff. :lol:

[Geo]

I think you're pointing at extreme Consequences of the "never let your shadow cross my path again!" variety. There are consequences short of that --and NV got a pretty good taste of that for a couple years there.
Pffft! They walked and were more than gladly helped to walk away from that fiasco of theirs, very few held/hold them accountable.

I'm still disgusted over a number of places and how they dealt/deal with that. :?

They didn't get the death penalty because it wasn't a capital crime. By my view, they still did get to play "hide the soap" with Bubba at the county lockup for a one year tour or so. Now they are rehabilitated, paid their debt to society, and ready to be a productive member of the community again. Next case, please.

That some were still writing them love letters while they were in prison is a different phenomenon. I recently read that Scott Peterson has already had two marriage proposals since his conviction. This should not be confused with how most people saw it.

But we are getting far afield.

[Farid]

They didn't get the death penalty because it wasn't a capital crime. By my view, they still did get to play "hide the soap" with Bubba at the county lockup for a one year tour or so. Now they are rehabilitated, paid their debt to society, and ready to be a productive member of the community again. Next case, please.

That some were still writing them love letters while they were in prison is a different phenomenon. I recently read that Scott Peterson has already had two marriage proposals since his conviction. This should not be confused with how most people saw it.

But we are getting far afield.
:lol: Excellent post.

[Chalnoth]

You ever lean back in your chair really far to just about as far back as you can balance yourself without falling over backwards? Then you lean back just a little bit more and start to go over backwards but with a jerk of your body recover your balance just before falling over? You know how you feel when that little jerk hits?
See, my brother made a habit of this. He ended up with a broken chair.

[Geeforcer]

Unstated (mostly) support for this position is the specter of the con-job ATI did last time with specs in lead-up days. I believe our gracious host was fed (whether it was directly, or indirectly thru partners, I'm not sure) that line o' bull last time, and might be being fed misinformation again --tho how much he actually believed, this time or last, only he can say.

Is this in reference to R420? Because most of the late rumors were pretty much dead-on.

[Chalnoth]

Not long before the announcement of the R420 people were still bandying about "eight extreme pipelines."

[digitalwanderer]

See, my brother made a habit of this. He ended up with a broken chair.
Really? Oddly enough my brother did too, but he ended up with a busted tailbone. (True story! :lol: )

[Tim Murray]

You ever lean back in your chair really far to just about as far back as you can balance yourself without falling over backwards? Then you lean back just a little bit more and start to go over backwards but with a jerk of your body recover your balance just before falling over? You know how you feel when that little jerk hits?
See, my brother made a habit of this. He ended up with a broken chair.
I think that's why the dorm chairs can rock back slightly. Yet I still rock past where it's supposed to be able to. It's fake rocking otherwise. :)

[ANova]

Now they are rehabilitated, paid their debt to society, and ready to be a productive member of the community again. Next case, please.

I don't consider spreading FUD to try to sell more of their products, which they knew were FUBARed (and which they succeeded in doing because of all the loyal sheeple) rather then owning up to their mistakes, having their debt to society paid up.

They continued to do the same with their playing up of SM3 (most notibly the now famous SM3 vs SM2 FC shots which were actually SM3 vs SM1.1). The 3dmark03 benchmark showing some rediculously high number for the 6800 Ultra only to later find they had run it in 8x6 but of course failed to mention that. The 'leaked internal' PPT presentation bashing ATI with more FUD and complete bs making them look like 10 year olds followed by their accusation that the R420 was 3 year old technology. Need I go on?

Just because the 6800 series is a decent card doesn't mean they are all paid up in my books. They are still the same coniving, turd throwing company they have always been.

Sorry, had to get that off my chest. :twisted:

[Geo]

Just because the 6800 series is a decent card doesn't mean they are all paid up in my books. They are still the same coniving, turd throwing company they have always been.

Sorry, had to get that off my chest. :twisted:

Hey, no problem --the B3D Encounter Group is full-service. Some people won't hire ex-cons --some will, and some of those factor in how long since the last conviction in making the determination. :lol:

But I'm stopping now on this topic before the gendarmes show up for my misdemeanor (on this thread at least) @ss! :wink:

[Geeforcer]

Not long before the announcement of the R420 people were still bandying about "eight extreme pipelines."

No, the extreme pipelines was quite an old rumor/news. We knew it would be a 16-pipeline R300-baded card with SM 2.0 a few weeks before NV40 launch.

[Geo]

Not long before the announcement of the R420 people were still bandying about "eight extreme pipelines."

No, the extreme pipelines was quite an old rumor/news. We knew it would be a 16-pipeline R300-baded card with SM 2.0 a few weeks before NV40 launch.

Define "few", and are we in that same window now re:R520 --my memory says not. Tho "we knew" can be squishy in these cases too, as unless the source is impeccable there is usually a transition period of jettisoning the old rumors for the new where it wouldn't be fair to put a date on "we knew" until that process was more or less complete (i.e. had been accepted by a sizable minority with some "usually in the know" leadership buying-in publicly).

The relationship to NV40 release is interesting too, as I seem to recall that NV40 details were leaking, and as they were closer to launch than ATI were presumed to be relatively accurate --which then put pressure on ATI to respond with the truth while reducing their exposure for doing so (because NV40 details were already out there). That dynamic doesn't exist right now.

Which is *not* to say that Dave and others have been the recipients of misinformation this time around --I'm just saying that given the record it is too early to have confidence that they haven't, unless they wish to speak to the issue with some detail, which would surprise (and delight --so long as it didn't get them in trouble) me.

[MuFu]

Where's CMKRNL when you need him? ;)

The big personal turnaround re. R420 was getting sucked into the PS3.0 hype, despite having been told it was very unlikely to support it by someone who worked on the hardware in H1 '03. Doh. The "8 extreme pipelines" idea tied in with hearing from devs who had extracted fillrate figures corresponding to an 8-pipe design from an NV40 ES (obviously, in hindsight, with 2 quads disabled). I have been busy getting a life since then. :lol:

[Chalnoth]

No, the extreme pipelines was quite an old rumor/news. We knew it would be a 16-pipeline R300-baded card with SM 2.0 a few weeks before NV40 launch.
This thread (http://www.beyond3d.com/forum/viewtopic.php?t=10248&start=0) wasn't too long before the NV40 launch, and many people were assuming that the R420 would have SM3 support.

[Geeforcer]

Chalnoth, geo: Few weeks I mean over a month. I for one recall INQ story/thread here about R420 being a 16-pipeline part after the rumors of 16-pipeline NV40. From my recollection, there was consensus that it will A)have 16-pipelines (that part was all but officaly confimed) and B) have PS 2.0 and VS 3.0, which falls under close enough.

[Chalnoth]

Chalnoth, geo: Few weeks I mean over a month. I for one recall INQ story/thread here about R420 being a 16-pipeline part after the rumors of 16-pipeline NV40.
I doubt you could call that a credible rumor, considering it's just like, "Oh, well, nVidia did it, so ATI must be doing it."

From my recollection, there was consensus that it will A)have 16-pipelines (that part was all but officaly confimed) and B) have PS 2.0 and VS 3.0, which falls under close enough.
It didn't have VS 3.0, and there didn't look like any consensus to me, looking back. PS 2.0 was about the most solid piece of info out there, due to ATI statements and Ashli shader support. But everything else was essentially up in the air, with nothing really known, like exactly what options in SM2 ATI would support (most people thought it'd be a much larger change than it actually was, even those who thought it was a SM2 part).

Hell, many people were even doubtful about ATI's SM2.0b support even after the NV40 launch, where we saw information about the SM2.0b profile.

Here are some threads from around that time frame:
http://www.beyond3d.com/forum/viewtopic.php?t=10967
http://www.beyond3d.com/forum/viewtopic.php?t=10401
http://www.beyond3d.com/forum/viewtopic.php?t=9868

Anyway, the key is that yes, there were indeed rumors that were spot-on. But there were many, many more that were just way the hell off.

[kemosabe]

I have been busy getting a life since then. :lol:

Hey, there's much to be said for getting a life. Some of us were contending with just that when R420 was in the blender and this place was a torture chamber for anyone who wasn't under NDA. So I guess we all get to be surprised (or not) as a big happy geek family this time. :lol:

[digitalwanderer]

I have been busy getting a life since then. :lol:

Hey, there's much to be said for getting a life.
There are also numerous drawbacks and it can suck up all your time quite quickly.

(What in the hell was I thinking of getting three puppies at once!?!?! :? )

[ANova]

I have been busy getting a life since then. :lol:

Hey, there's much to be said for getting a life.
There are also numerous drawbacks and it can suck up all your time quite quickly.

(What in the hell was I thinking of getting three puppies at once!?!?! :? )

Whoa, you got three puppies in addition to kids? :shock:

What were you thinking man. :wink:

[digitalwanderer]

Whoa, you got three puppies in addition to kids? :shock:

What were you thinking man. :wink:
Puppies would be easier? :oops:

They're actually pretty damned terrific, but it is also a pretty good example of how life can eat up your time too. (And shoes, coat, pants, carpet, bed, wall, cupboard, headphones, mouse, etc....but none of the leather living room set yet, knock-wood! :? )


So I heard the new R520 will support WGF and have 16 extreme pipelines....

[Geo]

So I heard the new R520 will support WGF and have 16 extreme pipelines....

Yeah, the breathless news flashes at Inq on WGF support are priceless. Right up there with "Interesting Canadian Initiative" in the headline writing world (apropos of absolutely nothing relevant here, alltime fave headline anywhere/when --a decapitation at a strip joint-- "Headless Body in Topless Bar".)

[digitalwanderer]

Did I mention it's going to have extreme WGF support? :|

[Unknown Soldier]

Isn't it supposed to be 24 Extreme Pipelines??

US ;)

[Megadrive1988]

so, R520 Fudo has WGF 1.0 support - DX9.0+ ... slightly *beyond* the DX9.0c spec, aka DX9.L (L for Longhorn) with SM3.0

then WGF2.0 which is DirectX10 aka DirectX Next will be supported in R600 (or R620) with SM4.0


????

http://www.theinquirer.net/?article=21982

[Tim Murray]

Is that like DX9.1? Diggy, won't that double GFFX performance?

[Pete]

Wasn't WGF 1.0 SM2?

/me scratches head

[Megadrive1988]

Wasn't WGF 1.0 SM2?

/me scratches head


I am not sure if WGF 1.0 was Shader Model 2.0 or both 2.0 and 3.0.

maybe it was 2.0 but is now 3.0 ?

[vb]

question:

If 8x vertex pipelines part is lifted off R500, do you think it will be able to run PS?

in that case it will have 24 pipelines

[oeLangOetan]

question:

If 8x vertex pipelines part is lifted off R500, do you think it will be able to run PS?

in that case it will have 24 pipelines
there are no vertex pipelines on the R500

[vb]

there are no vertex pipelines on the R500

Did I say there are any?

[Ailuros]

Nobody thinks 16p/8v@650-700MHz with a big per-clock efficiency improvement? Keeping the ALUs busy will have received a massive design push since the day they started working on a unified architecture.

I've heard 16@650MHz, but in the weeks running up to the R420 launch the word was of a 12-pipe part. So who knows...

I do sir :)

[MuFu]

Good stuff. The only update that I've heard to that unconfirmed line of speculation is that samples have exceeded target clocks (for the high-end SKU anyway; >650MHz).

[caboosemoose]

I would say about 550MHz with 24 pipes is feasible, while each pipe should have at least x1.3 the performance of one R480-pipe. R580 should then be to R520 what R480 was to R420.

Not exactly - R580 is slated to have 150% of the performance of R520, so the delta is much bigger than that between R420 and R480. In fact, R580 is actually a differenent architecture, I'm not sure exactly how, but it has additonal circuitry, although it also remians a 16 pipe part according to my info. In fact, from my info I'm expecting R580 to be the part with the "fat" pipes rather than R520.

[Ailuros]

No, the extreme pipelines was quite an old rumor/news. We knew it would be a 16-pipeline R300-baded card with SM 2.0 a few weeks before NV40 launch.
This thread (http://www.beyond3d.com/forum/viewtopic.php?t=10248&start=0) wasn't too long before the NV40 launch, and many people were assuming that the R420 would have SM3 support.

I don't recall Wavey specifically supporting that theory (or the extreme pipeline stuff) neither in the linked thread nor anywhere else.

If 8x vertex pipelines part is lifted off R500, do you think it will be able to run PS?

in that case it will have 24 pipelines

How can you lift "any" vertex-whatever from R500 when it's going to have unified shader units? It looks like 4 quads or 16 SIMD channels if you prefer, whereby each SIMD channel can be dynamically used for either PS or VS calls.

[MuFu]

I would say about 550MHz with 24 pipes is feasible, while each pipe should have at least x1.3 the performance of one R480-pipe. R580 should then be to R520 what R480 was to R420.

Not exactly - R580 is slated to have 150% of the performance of R520, so the delta is much bigger than that between R420 and R480. In fact, R580 is actually a differenent architecture, I'm not sure exactly how, but it has additonal circuitry, although it also remians a 16 pipe part according to my info. In fact, from my info I'm expecting R580 to be the part with the "fat" pipes rather than R520.

I have heard something to that effect as well. Rather confusingly it suggests 3 TMUs per pipe so I'm not sure what to make of it. :?

[Ailuros]

Good stuff. The only update that I've heard to that unconfirmed line of speculation is that samples have exceeded target clocks (for the high-end SKU anyway; >650MHz).

Errr....how rare is that going to be? :roll:

Not exactly - R580 is slated to have 150% of the performance of R520, so the delta is much bigger than that between R420 and R480. In fact, R580 is actually a differenent architecture, I'm not sure exactly how, but it has additonal circuitry, although it also remians a 16 pipe part according to my info. In fact, from my info I'm expecting R580 to be the part with the "fat" pipes rather than R520.

50% more performance (at least theoretically) compared to R520 sounds feasable to me. I don't see why it would need any significant architectural changes either. R580 sounds more like a part to me that will have GDDR4 and thus much more bandwidth than R520.

[MuFu]

Good stuff. The only update that I've heard to that unconfirmed line of speculation is that samples have exceeded target clocks (for the high-end SKU anyway; >650MHz).

Errr....how rare is that going to be? :roll:

I have no idea. How can we possibly tell at this stage?

My ninja-editing skills need work. :x

[caboosemoose]

I would say about 550MHz with 24 pipes is feasible, while each pipe should have at least x1.3 the performance of one R480-pipe. R580 should then be to R520 what R480 was to R420.

Not exactly - R580 is slated to have 150% of the performance of R520, so the delta is much bigger than that between R420 and R480. In fact, R580 is actually a differenent architecture, I'm not sure exactly how, but it has additonal circuitry, although it also remians a 16 pipe part according to my info. In fact, from my info I'm expecting R580 to be the part with the "fat" pipes rather than R520.

I have heard something to that effect as well. Rather confusingly it suggested 3 TMUs per pipe. Sounds like the kind of thing that some people might run with and get dangerously excited. :?

Correct, my info seems to indicate 3 TMUs per pipe. Running with that theme, my info indicates that RV530 will be a four fat pipe part with 3 TMUs per pipe and will offer around 50% the performance of R520. RV530 will also have a doubling of some area of architecture that I can't indentify from my info. Essentially my information describes R520 as: 16-1-1-1, RV530 as: 4-1-3-2 and R580 as 16-1-3-1 - oh, and RV515 as 4-1-1-1. I have not key for this particular syntax so other than the reasonable safe assumption that the first figure is pipeplines the rest is speculation to a degree.

Oh and if you care about such things my info also indicates that R520 taped out slightly under a year ago and that R580 taped towards then end of last year.

[Ailuros]

Well we are speculating after all aren't we? :wink:

Of course would it be ideal to have >650MHz samples in adequate quantities, but since this is the first low-k 90nm VPU, the odds weigh more into the benchmark winning/ultra-rare direction for very high frequencies IMHO.

[MuFu]

Oh and if you care about such things the document indicates that R520 taped out slightly under a year ago and that R580 taped towards then end of last year.

I think we need to see this "document" of yours. :lol:

Well we are speculating after all aren't we? :wink:

Yeah we'd better STFU about unchartered yield characteristics, lol.

[caboosemoose]

Oh and if you care about such things the document indicates that R520 taped out slightly under a year ago and that R580 taped towards then end of last year.

I think we need to see this "document" of yours. :lol:

Yeah, let's not even go there, I'm not going to make any attempt to convince anyone of anything, it's take it or leave it.

[MuFu]

I'll take it then, please.

[Ailuros]

Essentially the document describes R520 as: 16-1-1-1, RV530 as: 4-1-3-2 and R580 as 16-1-3-1 - oh, and RV515 as 4-1-1-1. There's no key so other than the reasonable safe assumption that the first figure is pipeplines the rest is speculation to a degree.

Probably dumb question, but how sure are you that the 3rd number for each model actually signifies TMUs? Does the document in question explain something relevant, or are you rather speculating?

To make things clear with the bandwidth I'd expect for R580 (=/>65GB/sec), >16TMUs make sense; what I'm having a hard time understanding is the odd number of TMUs in such a case.

Are you sure those aren't ALUs f.e.? I'd rather think of:

SIMD channel / ROP / ALU / TMU

[caboosemoose]

Essentially the document describes R520 as: 16-1-1-1, RV530 as: 4-1-3-2 and R580 as 16-1-3-1 - oh, and RV515 as 4-1-1-1. There's no key so other than the reasonable safe assumption that the first figure is pipeplines the rest is speculation to a degree.

Probably dumb question, but how sure are you that the 3rd number for each model actually signifies TMUs? Does the document in question explain something relevant, or are you rather speculating?

To make things clear with the bandwidth I'd expect for R580 (=/>65GB/sec), >16TMUs make sense; what I'm having a hard time understanding is the odd number of TMUs in such a case.

Are you sure those aren't ALUs f.e.? I'd rather think of:

SIMD channel / ROP / ALU / TMU

I'm not sure of anything really. As I said, the first number looks an awful lot like fragment pipes, but as I said the rest is specualtion.

[Ailuros]

Well the "3"s can't be ROPs IMO; I'd guess that 16 ROPs are going to be plenty for the foreseeable future (even irrelevant to other possible competing sollutions with >4 quads).

[MuFu]

I went backwards from hearing "48 tex samplers" to get 3 per pipe, if you get my drift. Seems more likely to be the number of ALUs though.

RV530 as: 4-1-3-2 and R580 as 16-1-3-1

Looking at that, it might make sense for the first figure to be ROPs and the last, SIMD channels per "pipeline".

How many times have we had discussions like this? Wow.

[Dave Baumann]

Last value is Z/Stencil.

[Xmas]

ATI has been stating several times in the past that the ALU to TMU ratio is only going to grow. Maybe the 1.3 figure is just a hint at an odd number of TMUs vs. number of ALUs.

[Dave Baumann]

Or just more flexible texture samplers that are tailored differently to current ones to cope with increasing float sampling demands.

[Ailuros]

Last value is Z/Stencil.

Hmmm.....

SIMD channel / TMU / ALU / ROP then? :lol:

[Dave Baumann]

No, third value it texture sampling abilities.

[MuFu]

Last value is Z/Stencil.

Hmmm.....

SIMD channel / TMU / ALU / ROP then? :lol:

Why would RV530 have >1 ROP per pipe though?

[incurable]

So it's ROPs / ??? / tex / Z or is ATi just pulling our collective legs again? :?

[tEd]

So it's ROPs / ??? / tex / Z or is ATi just pulling our collective legs again? :?

pipe - tex/alu/z per cycle would make more sense IMO

what i can't really believe is that r580 supposed be taped out last year already

[Ailuros]

No, third value it texture sampling abilities.

Why an odd number then? Is that in any way related to vertex texturing maybe?

Why would RV530 have >1 ROP per pipe though?

Good question. Dave already helped getting the numbers into place. Even if, 8 ROPs wouldn't necessarily hurt on a mainstream part IMO, especially if one would yield higher multisampling performance than usual or not?

[incurable]

So it's ROPs / ??? / tex / Z or is ATi just pulling our collective legs again? :?

pipe - tex/alu/z per cycle would make more sense IMO
I just don't see that, it would mean that ATi's next-gen mid-range product (RV530) would only have 4 pipes. An NV43-like construct with a larger number of pipes feeding a 128-bit (?) memory interface through 4 ROPs seems more likely. I wonder if the '3' in the tex column could be an indication for the number of shader pipes. *hmm*

[tEd]

Maybe they don't have a seperate texture units on r580 anymore like nv40.

[PatrickL]

If the R580 was really taped out in december, what could be the point in releasing the 520 ?

In fact I wonder if the past pages are not just a giant farce :wink:

[caboosemoose]

If the R580 was really taped out in december, what could be the point in releasing the 520 ?

In fact I wonder if the past pages are not just a giant farce :wink:

Well, becuase at any given point several chips are in various stages of development, it doesn't make sense to say that because R580 has taped that there's no pointin releasing R520 - just because R580 has allegedly taped doesn't mean it's ready to roll. There's plenty of work to be done following the first tape out, hence that work has probably been completed on R520 and so that chip is probably very nearly ready to go.

[madshi]

No, third value it texture sampling abilities.
That would mean R580 had 3 times the texture sampling power of R520, while the ALU power stays the same? Sounds strange to me...

[tEd]

No, third value it texture sampling abilities.
That would mean R580 had 3 times the texture sampling power of R520, while the ALU power stays the same? Sounds strange to me...

this could actually be a combo tex/alu functionality

[Geo]

Good stuff. The only update that I've heard to that unconfirmed line of speculation is that samples have exceeded target clocks (for the high-end SKU anyway; >650MHz).

Assuming that is relatively repeatable and not a freak of nature, that would support the less-pipes side of the scale wouldn't it?

[Jawed]

So R580 is the one with the 512-bit bus.

Hey maybe it also has 1 TMU dedicated to floating point texturing...

And what about that final number being the number of pipes sharing a ROP. Wouldn't it make sense that the value part has 2 pipes per ROP?

Jawed

[Dave Baumann]

No, third value it texture sampling abilities.
That would mean R580 had 3 times the texture sampling power of R520, while the ALU power stays the same? Sounds strange to me...

this could actually be a combo tex/alu functionality

ALU's are fairly large, would they really be able to triple the ALU performance on a refresh?

As I said before though, the samplers may just be more flexible not necessarily have the same performance between R520 and 580 (on a "per quoted texture unit" basis).

[_xxx_]

So R580 is the one with the 512-bit bus.

I just don't get it why anyone would want to go through pains of implementing/designing boards with 512-bit bus when there already are serial solutions like the Rambus tech in PS3 which are just as fast or faster and much easier to implement :?

[Jawed]

So R580 is the one with the 512-bit bus.

I just don't get it why anyone would want to go through pains of implementing/designing boards with 512-bit bus when there already are serial solutions like the Rambus tech in PS3 which are just as fast or faster and much easier to implement :?

Maybe that has to do with licensing costs? GDDR3 is practically ATI tech (that's how it seems to me). I suppose ATI has some investment in GDDR4.

Erm, I dunno, wild guesses.

Jawed

[Rys]

I hazily remember seeing numbers like that written on a napkin in a hotel bar, a while back. I should start paying attention.

[_xxx_]

I suppose the licensing would cost much less than the implementation of 512-bit bus. Just think of the pincounts and the layout of such a board. Even more layers, more problems in _every_ area. Scary, I really don't envy the board designers there.

[tEd]

No, third value it texture sampling abilities.
That would mean R580 had 3 times the texture sampling power of R520, while the ALU power stays the same? Sounds strange to me...

this could actually be a combo tex/alu functionality

ALU's are fairly large, would they really be able to triple the ALU performance on a refresh?

As I said before though, the samplers may just be more flexible not necessarily have the same performance between R520 and 580 (on a "per quoted texture unit" basis).

i don't think fully triple the alu performance but the 3 not necessary have to indicate 3 full alus or 3 tex. Maybe it has 2full alus with a combo tex/alu unit but with limited alu capabillitites(mini alu) or having 2full alus and 1 tex but can only issue either 2alu ops or 1alu/1tex ops per cycle

I don't think this is impossible and frankly r580 doesn't look like typical refresh to me anyway but of course it's just a guess and very well BS

[chavvdarrr]

1 simple question
When are we going to know more info on R520? The whole thread seems... strange. Do we expect announcement before the end of March or just some people need to post in such thread every now and then?

[digitalwanderer]

Is that like DX9.1? Diggy, won't that double GFFX performance?
Yup, and quadritouple the Rxxx series performance too. http://mastabeta.com/forum/images/smilies/yep.gif

I have it on good authority from Team DX....

[Megadrive1988]

So it's ROPs / ??? / tex / Z or is ATi just pulling our collective legs again? :?

pipe - tex/alu/z per cycle would make more sense IMO

what i can't really believe is that r580 supposed be taped out last year already

I can, since it cannot be much of an upgrade over r520, just a tweak, revision, speed bump. although December 2004 *is* actually pretty early.

maybe that means R520 will be ready to go sooner. like April-May, and then R580 in the fall.

[Megadrive1988]

I would say about 550MHz with 24 pipes is feasible, while each pipe should have at least x1.3 the performance of one R480-pipe. R580 should then be to R520 what R480 was to R420.

Not exactly - R580 is slated to have 150% of the performance of R520, so the delta is much bigger than that between R420 and R480. In fact, R580 is actually a differenent architecture, I'm not sure exactly how, but it has additonal circuitry, although it also remians a 16 pipe part according to my info. In fact, from my info I'm expecting R580 to be the part with the "fat" pipes rather than R520.

I have heard something to that effect as well. Rather confusingly it suggests 3 TMUs per pipe so I'm not sure what to make of it. :?


whoa! :shock:

I was thinking that, surly R580 was only going to be a minor tweak of R520 like R350 to R360 or R420 to R480.

but it does make sense that R580 is now probably a significant boost over R520 especially if Nvidia has G70 and even faster/more powerful G80 coming down this year.


heh, the graphics wars & one-upmanship NEVER end :P

[tEd]

So it's ROPs / ??? / tex / Z or is ATi just pulling our collective legs again? :?

pipe - tex/alu/z per cycle would make more sense IMO

what i can't really believe is that r580 supposed be taped out last year already

I can, since it cannot be much of an upgrade over r520, just a tweak, revision, speed bump. although December 2004 *is* actually pretty early.

maybe that means R520 will be ready to go sooner. like April-May, and then R580 in the fall.

r580 being just a simple refresh in ati terms , taped out in dec.04 seems really early to me but maybe they just planned with a longer timespan this time because of the new process. This could mean they taped out 3 0.09um SM3.0 parts in 04 :o

[caboosemoose]

So it's ROPs / ??? / tex / Z or is ATi just pulling our collective legs again? :?

pipe - tex/alu/z per cycle would make more sense IMO

what i can't really believe is that r580 supposed be taped out last year already

I can, since it cannot be much of an upgrade over r520, just a tweak, revision, speed bump. although December 2004 *is* actually pretty early.

maybe that means R520 will be ready to go sooner. like April-May, and then R580 in the fall.

r580 being just a simple refresh in ati terms , taped out in dec.04 seems really early to me but maybe they just planned with a longer timespan this time because of the new process. This could mean they taped out 3 0.09um SM3.0 parts in 04 :o

Well, I just think that there's a larger gap between intial tape out and launch than conventional wisdom dictates, rather than this latest generation being anything unusual.

[Dave Baumann]

Take a guess when ATI first recieved R520 back...

[digitalwanderer]

Take a guess when ATI first recieved R520 back...
When they received the first one back from the fab? Over a year ago.

[caboosemoose]

Take a guess when ATI first recieved R520 back...
When they received the first one back from the fab? Over a year ago.

Anyone feel like giving their idea of the definition of taped-out?

[tEd]

Take a guess when ATI first recieved R520 back...
When they received the first one back from the fab? Over a year ago.

Anyone feel like giving their idea of the definition of taped-out?

"Tape out" is the very first time a the chip layout is submitted to the fab. "Cycle Time" is the time for each submission of a design to the fab to come back from the fab fab as a wafer

that was a copy/paste :oops:

cycle time usually 6-8weeks

[caboosemoose]

Take a guess when ATI first recieved R520 back...

July - August last year.

[Megadrive1988]

Take a guess when ATI first recieved R520 back...


many months before December :lol:

[jb]

Take a guess when ATI first recieved R520 back...

Why, whould you even tell us if we were close? :) :) :) :)


Where's CMKRNL when you need him? ;)


You should change that to:
Where's CMKRNL when you need her?

Of course I could be way off, BUT I thought CMKRNL was a female...

[digitalwanderer]

Why, whould you even tell us if we were close? :) :) :) :)
No. http://mastabeta.com/forum/images/smilies/yep.gif

[jb]

Why, whould you even tell us if we were close? :) :) :) :)
No. http://mastabeta.com/forum/images/smilies/yep.gif

So true and yet so hard to resit playing his game... Curse you Dave (in a good way of course)

[Megadrive1988]

I would say about 550MHz with 24 pipes is feasible, while each pipe should have at least x1.3 the performance of one R480-pipe. R580 should then be to R520 what R480 was to R420.

Not exactly - R580 is slated to have 150% of the performance of R520, so the delta is much bigger than that between R420 and R480. In fact, R580 is actually a differenent architecture, I'm not sure exactly how, but it has additonal circuitry, although it also remians a 16 pipe part according to my info. In fact, from my info I'm expecting R580 to be the part with the "fat" pipes rather than R520.

I have heard something to that effect as well. Rather confusingly it suggested 3 TMUs per pipe. Sounds like the kind of thing that some people might run with and get dangerously excited. :?

Correct, my info seems to indicate 3 TMUs per pipe. Running with that theme, my info indicates that RV530 will be a four fat pipe part with 3 TMUs per pipe and will offer around 50% the performance of R520. RV530 will also have a doubling of some area of architecture that I can't indentify from my info. Essentially my information describes R520 as: 16-1-1-1, RV530 as: 4-1-3-2 and R580 as 16-1-3-1 - oh, and RV515 as 4-1-1-1. I have not key for this particular syntax so other than the reasonable safe assumption that the first figure is pipeplines the rest is speculation to a degree.

Oh and if you care about such things my info also indicates that R520 taped out slightly under a year ago and that R580 taped towards then end of last year.


I'd be really impressed if this is ATI's route. especially after the dissapointingly small leaps of R350 and R360 over R300, as well as R480 over R420.

[digitalwanderer]

So true and yet so hard to resit playing his game... Curse you Dave (in a good way of course)
The man is good, I gotta admit. No one knows how to whip some speculations into a frenzy pre-launch the way good old Dave does. :)

[Megadrive1988]

So R580 is the one with the 512-bit bus.

Hey maybe it also has 1 TMU dedicated to floating point texturing...

And what about that final number being the number of pipes sharing a ROP. Wouldn't it make sense that the value part has 2 pipes per ROP?

Jawed


512-bit bus for R580 ??? you said "so R580 is the one with the 512-bit bus"

I am assuming Jawed, that you were aware of some ATI VPU on a roadmap with 512-bit bus? whatever it was you got to see (roadmap, post, website, etc) can I see too ? :)

[MuFu]

Take a guess when ATI first recieved R520 back...

Why, whould you even tell us if we were close? :) :) :) :)


Where's CMKRNL when you need him? ;)


You should change that to:
Where's CMKRNL when you need her?

Of course I could be way off, BUT I thought CMKRNL was a female...

Well I started that load of nonsense so have the right to un-start it. :lol:

I believe R520 came back in early December. What is suprising is the lack of new info after CeBIT. You would have thought that all that beer would have loosened a few NDA-monkeys up a little. I bet more than a couple of employees woke up with that "OMG what did I tell Fuad?" feeling. :D

[mikechai]

Take a guess when ATI first recieved R520 back...

Before X800XT PE actually available.

[Geo]

I bet more than a couple of employees woke up with that "OMG what did I tell Fuad?" feeling. :D

Dude clearly isn't technical. If I was an IHV employee on the way to one of those shindigs I'd load up on esoteric DX7 tidbits and dribble 'em out "confidentially" as elements that the next gen will support. . .keep meself in free beers all night. :D

[wireframe]

In all this speculation, is there any terra firma that you are all holding as an absolute truth? It seems the ball is just bouncing from side to side and there is very little to suggest one line of thought is better or more accurate than another.

In accepting or disregarding the original information are you rejecting it all?

I think the 300-350 million transistor count sounds reasonable. I base this on a investor conference call when there was apparently some debate about how costly this line would be to produce. IIRC there was mention that the overall die size would be approximately the same as the current R420 even with all the goodies proposed. Unless I am completely mistaken, a 90nm process should give you roughly twice the number of transistors in the same die area when compared to 130nm. So, does anyone else think that the 300M+ transistor R520 holds any water? It may be a good place to start. Of course there would still be lots of 'splainin' to do...Lucy... :P

[Geo]

1 simple question
When are we going to know more info on R520? The whole thread seems... strange. Do we expect announcement before the end of March or just some people need to post in such thread every now and then?

Hey, here in America it is spring training for the national pastime. The greatest in the world at what they do are stretching their muscles after a winter of rest, working on their timing, and building their wind for the long campaign to come.

So are we. :D

[digitalwanderer]

Well I started that load of nonsense so have the right to un-start it. :lol:
Now I didn't think I missed anything around here, but just what is all this CMKRNL talk about? :|

I believe R520 came back in early December. What is suprising is the lack of new info after CeBIT. You would have thought that all that beer would have loosened a few NDA-monkeys up a little. I bet more than a couple of employees woke up with that "OMG what did I tell Fuad?" feeling. :D
Yes, but I bet a lot of the Fuads were pretty well into their own cups at the time and might not remember either. ;)

Although the lack of info is weird, I'll agree...kind of like before the launch of the R420.... :?

[Jawed]

So R580 is the one with the 512-bit bus.

Hey maybe it also has 1 TMU dedicated to floating point texturing...

And what about that final number being the number of pipes sharing a ROP. Wouldn't it make sense that the value part has 2 pipes per ROP?

Jawed


512-bit bus for R580 ??? you said "so R580 is the one with the 512-bit bus"

I am assuming Jawed, that you were aware of some ATI VPU on a roadmap with 512-bit bus? whatever it was you got to see (roadmap, post, website, etc) can I see too ? :)

Teehee, I hope you realise I'm just an on-looking speculator, like most of this thread's participants.

The only reason I say 512-bit is because of the idea of GDDR4 (coming real soon now, end of the year) and the bandwidth crunch that can only get worse with the next generation VPUs. If R580 has all that texturing power (3xTMUs per pipeline? One a floating point unit?) it's gonna need an awful lot of bandwith.

At the same time this question of Rambus tech is pretty intriguing. Wouldn't it be interesting if NVidia peeled away from GDDR tech to implement XDR in 2006 on PC parts, having gained experience with this tech by working on PS3?

Jawed

[kemosabe]

So true and yet so hard to resit playing his game... Curse you Dave (in a good way of course)
The man is good, I gotta admit. No one knows how to whip some speculations into a frenzy pre-launch the way good old Dave does. :)

Just keep politely insinuating that he really seems to know nothing more than anyone else. Sooner or later the verbal incontinence will overwhelm him. :wink: :lol:

[digitalwanderer]

What, you don't really think Dave knows anything about the R520...do you?

From what I've been hearing he's been out of the ATi loop ever since that debacle of his.... :?

[Geo]

Personally, that 300-350m transistor count is why I keep going loop-de-loop in my own brain on this issue. Dave is certainly leaning in a direction. . .and I don't see how that direction fits with that transistor count without some pretty signficant changes in the architecture. . .yet we aren't getting a whiff of that kind of fundamental change this time around from anywhere but Dave (that I've seen at least). Yet, in my mind, there's a "reasonablity" test that says to me if you're gonna make that kind of big change with a minimum of risk to performance that having a whole buncha more transistors available to do it with like a major process change is the time to do it.

Then I go waaaaay back to the original R400 rumors, and Orton smirking in public that the R300 tweren't nuttin', it was R400 that had him excited. . .and a little later rumors that they'd canned R400 in part because they'd regrettably come to the conclusion it was too ambitious for the process available at the time. . .

Well, I bet it wasn't too ambitious for 90nm.

So, no, no terra firma in my cupboard, thanks for asking.

[Sunrise]

If the R580 was really taped out in december, what could be the point in releasing the 520 ?

In fact I wonder if the past pages are not just a giant farce :wink:

Bandwidth needs and availability of sufficient amounts of high-speed memory in a planned timeframe you want to release a chip. R520 will therefore not have everything enabled, or should i say, will be / is a cut down version (quads / ROPs) of something (R580) they want to release later (but very similiar in overall technology).

[madshi]

From what I've been hearing he's been out of the ATi loop ever since that debacle of his.... :?
You mean the one with the laser pointer? :D

[caboosemoose]

Personally, that 300-350m transistor count is why I keep going loop-de-loop in my own brain on this issue. Dave is certainly leaning in a direction. . .and I don't see how that direction fits with that transistor count without some pretty signficant changes in the architecture. . .yet we aren't getting a whiff of that kind of fundamental change this time around from anywhere but Dave (that I've seen at least). Yet, in my mind, there's a "reasonablity" test that says to me if you're gonna make that kind of big change with a minimum of risk to performance that having a whole buncha more transistors available to do it with like a major process time is the time to do it.

Then I go waaaaay back to the original R400 rumors, and Orton smirking in public that the R300 tweren't nuttin', it was R400 that had him excited. . .and a little later rumors that they'd canned R400 in part because they'd regrettably come to the conclusion it was too ambitious for the process available at the time. . .

Well, I bet it wasn't too ambitious for 90nm.

So, no, no terra firma in my cupboard, thanks for asking.

Yeah, it was the transistor count thing that had me wondering how my "info" squared up. Hard to see how R520 could possibly be well over 300 million transistors and for my info to be correct. R580, just maybe, but not R520. Only time will tell.

[digitalwanderer]

From what I've been hearing he's been out of the ATi loop ever since that debacle of his.... :?
You mean the one with the laser pointer? :D
No, the noodle incident! :shock:

[Tweaker]

The only reason I say 512-bit is because of the idea of GDDR4 (coming real soon now, end of the year) and the bandwidth crunch that can only get worse with the next generation VPUs. If R580 has all that texturing power (3xTMUs per pipeline? One a floating point unit?) it's gonna need an awful lot of bandwith.

At the same time this question of Rambus tech is pretty intriguing. Wouldn't it be interesting if NVidia peeled away from GDDR tech to implement XDR in 2006 on PC parts, having gained experience with this tech by working on PS3?

Jawed

I remember, last year there were speculations about new memory interface for R520
http://www.beyond3d.com/forum/viewtopic.php?t=17663
and
http://www.beyond3d.com/forum/viewtopic.php?t=16376

[Dave Baumann]

Yeah, it was the transistor count thing that had me wondering how my "info" squared up. Hard to see how R520 could possibly be well over 300 million transistors and for my info to be correct. R580, just maybe, but not R520. Only time will tell.

And this goes back to what I said earlier - a texture unit and pixel outputs make up a tiny portion of a "pipeline", whats in them is what takes up the transistors these days and thats the big unknown.

[Geo]

And this goes back to what I said earlier - a texture unit and pixel outputs make up a tiny portion of a "pipeline", whats in them is what takes up the transistors these days and thats the big unknown.

Any guesstimates available anywhere for current gen transistors counts for all the various functional units per unit (i.e. "one ALU=~x")? Or is that one of those things Orton keeps under his pillow at night?

[MuFu]

The only reason I say 512-bit is because of the idea of GDDR4 (coming real soon now, end of the year) and the bandwidth crunch that can only get worse with the next generation VPUs. If R580 has all that texturing power (3xTMUs per pipeline? One a floating point unit?) it's gonna need an awful lot of bandwith.

At the same time this question of Rambus tech is pretty intriguing. Wouldn't it be interesting if NVidia peeled away from GDDR tech to implement XDR in 2006 on PC parts, having gained experience with this tech by working on PS3?

Jawed

I remember, last year there were speculations about new memory interface for R520
http://www.beyond3d.com/forum/viewtopic.php?t=17663
and
http://www.beyond3d.com/forum/viewtopic.php?t=16376

The key thing is that supposedly this is a major *internal* change - a revised topology to increase the efficiency of data movement between functional units. The extra transistors that go into this may well be "worth their weight" vs. those that might have gone into additional pixel quads etc.

With R300 they relaxed the transistor count limitation and went for performance. R420 saw more of the same, with a die shrink and duplication of existing logic allowing them to realise a huge increase in performance without an architectural overhaul.

While 520 is still apparently based on R3x0, you'd think that the focus would have shifted to performance-per-transistor, given the time they've had to work on it, the fact that they have to shoehorn SM3.0 support in there anyway and the parallel development with newer tech that we might see in R5x0/6x0. Plus they're using a new process for the first time - better the balanced approach, that mates per-clock improvements with a relatively modest clock increase, than something that relies too heavily on yields.

[Jawed]

I remember, last year there were speculations about new memory interface for R520
http://www.beyond3d.com/forum/viewtopic.php?t=17663
and
http://www.beyond3d.com/forum/viewtopic.php?t=16376

Ooh, I'd forgotten about virtual memory.

Jawed

[Geo]

Aw, f**k it. I'm going with the Wavey eyeblink semaphore. R520 is 16p/8v, 300m transistors, 600mhz core for the tippity-top end. It is *signficantly* different than R300 in its basic pipeline/units infrastructure/organization, with major elements from the original R400 gee-whiz, including bus changes. SM3.0, of course, and a few other flourishes. Incrementally (i.e. not revolutionary) nicer AA (I think they need better API support for a signficant change if I read Sireric right somewhere else where he said there was agreement the api is "broke").

It will kick NV heinie for several months to the delight of all ATI-ans, while NV'ers mutter "just you wait" to themselves for that golden day in Oct/Nov when we have a part from NV that we can compare it to to determine "who was right" (NV vs ATI) in designing a 90nm part.

Part of me leans higher on the clock (even if it means fewer transistors), as I suspect that round-robin bus likes high clocks to keep everybody fed.

Write it down. Take it to the bank. [and be laughed out of the lobby when they say "WHO told you?"]

[Tweaker]

I remember, last year there were speculations about new memory interface for R520
http://www.beyond3d.com/forum/viewtopic.php?t=17663
and
http://www.beyond3d.com/forum/viewtopic.php?t=16376

Ooh, I'd forgotten about virtual memory.

Jawed

I don't think that it's about virtual memory. Read second link...

[Hellbinder]

1 simple question
When are we going to know more info on R520? The whole thread seems... strange. Do we expect announcement before the end of March or just some people need to post in such thread every now and then?

Hey, here in America it is spring training for the national pastime. The greatest in the world at what they do are stretching their muscles after a winter of rest, working on their timing, and building their wind for the long campaign to come.

So are we. :D

Spring TRaining for the NFL does not start for several months. What Sport are you talking about? ;)

[Hellbinder]

Aw, f**k it. I'm going with the Wavey eyeblink semaphore. R520 is 16p/8v, 300m transistors, 600mhz core for the tippity-top end. It is *signficantly* different than R300 in its basic pipeline/units infrastructure/organization, with major elements from the original R400 gee-whiz, including bus changes. SM3.0, of course, and a few other flourishes. Incrementally (i.e. not revolutionary) nicer AA (I think they need better API support for a signficant change if I read Sireric right somewhere else where he said there was agreement the api is "broke").

It will kick NV heinie for several months to the delight of all ATI-ans, while NV'ers mutter "just you wait" to themselves for that golden day in Oct/Nov when we have a part from NV that we can compare it to to determine "who was right" (NV vs ATI) in designing a 90nm part.

Part of me leans higher on the clock (even if it means fewer transistors), as I suspect that round-robin bus likes high clocks to keep everybody fed.

Write it down. Take it to the bank. [and be laughed out of the lobby when they say "WHO told you?"]
Nope...

[se_rag]

At the same time this question of Rambus tech is pretty intriguing. Wouldn't it be interesting if NVidia peeled away from GDDR tech to implement XDR in 2006 on PC parts, having gained experience with this tech by working on PS3?

Jawed
G70 is using Rambus's yellowstone memory bus.
G70=PS3

[jb]

Now I didn't think I missed anything around here, but just what is all this CMKRNL talk about? :|

Hmmm Maybe young grasshopper that was before the Digi days :)

But IIRC CMKRNL is or was an employee of one of the TMSC fabs. And back in her day (again assuming that I was correct in remember CMKRNL gender which i am not 100% sure on) she would leak out very juicy tid-bits of information. For example the first nV30 fab issues we heard about (and thus wich lead up to the nv30 being late and allowing ATI R300 to be first) was posted by her. Pretty much everything she posted here was spot on.. have not seen her post in awhile :(

Again this is assuming I remembered my history correctly (which in my case is a toss up) :)

[MuFu]

jb, CMKRNL was a guy!

Hellbinder, what does your crystal ball say?

[Pete]

What I'd like to know is who's hitting this thread more: nV or ATi? :)

[tEd]

jb, CMKRNL was a guy!



Was a guy so is a woman now? :shock:

[Geo]

Nope...

Bah, I shall not be dissuaded.

Asynch clock for that bus, mebbee? Gonna go down, might as well do it swinging.

[MuFu]

What I'd like to know is who's hitting this thread more: nV or ATi? :)

And by hitting, you of course mean "laughing at...".

[digitalwanderer]

Thanks for the explanation JB! :)

As for laughing at, I'd say ATi is definately laughing at this one more right now...I don't think nVidia is laughing much about the R520 yet. :?

[Geo]

Thanks for the explanation JB! :)

As for laughing at, I'd say ATi is definately laughing at this one more right now...I don't think nVidia is laughing much about the R520 yet. :?

Hey, Digi, after a year of snide comments and powerpoints from NV about what an aging dinosaur R3/4xx architecture is, aren't you looking forward to six months of new snide material about the radically dangerous, performance-killing, "ATI's NV30" architecture? That would be better than mo' same-old/same-old. :D

[Pete]

And by hitting, you of course mean "laughing at...".But of coursh.

If caboosemoose's rumors are right, then nV would be laughing b/c they already have it. If they're wrong, then ATi would be laughing b/c we're so desparate. Either way, I think it's safe to say they're mean-spirited people. ;^)