CELL DIE

[version]

http://web.axelero.hu/varga1973/EE.JPG

this is Emotion Engine with 10.5 mills transistors

in CELL a PU about 5-10 mills trans, APU is 3-4 mills

4 PU= 20-40 mills trans
32 APU =90-130 mills

CELL 200 millions transistors with 32 APU and 4 PU and any cache
if APU speed is 4,6 GHZ then CELL compute 1.2 Tflops, and 2.4 Tips


this is possible?

[DeanoC]

Each APU is meant to have 128K SRAM, I'm not a hardware guy but isn't 128K something like 4 million transistors?

Your figures look wrong to me but I'm not a hardware guy so what do I know.

[version]

Each APU is meant to have 128K SRAM, I'm not a hardware guy but isn't 128K something like 4 million transistors?

Your figures look wrong to me but I'm not a hardware guy so what do I know.

you look emotion engine die, 2 VU and 40kb ram about 4 millions transistors !

[randycat99]

Just as an observation, it is amazing to see how little space the actual MIPs core occupies compared to the vector units and even just supporting interfaces (granted, other more pervasive CPU designs are typically only 1/2 of the area is actually "CPU" and the other 1/2 goes entirely to L2 cache space). The vector units themselves are the size of a whole other processor. I always imagined the vector units were just 2 smaller things hanging off a MIPs core. However, this illustration should give fair indication that it isn't a trivial matter to throw on a vector unit when it comes to how to use your die space. There is a design intent behind this stuff.

[passerby]

Have to say I like the title of the thread, it's refreshing - "Cell(,) DIE(!!!)" :twisted:

It may be more interesting to post the layout of the EE+GS @ 90nm for greater fun.

[V3]

Each APU is meant to have 128K SRAM, I'm not a hardware guy but isn't 128K something like 4 million transistors?

That cell SPU will use the 6 transistors memory cell, so that come at over 6 million transistors just for the memory alone (128k). More if they decided to give it more memory.

in CELL a PU about 5-10 mills trans, APU is 3-4 mills

4 PU= 20-40 mills trans
32 APU =90-130 mills

CELL 200 millions transistors with 32 APU and 4 PU and any cache
if APU speed is 4,6 GHZ then CELL compute 1.2 Tflops, and 2.4 Tips

The current cell is only one PU and undisclosed number of SPUs (lets assume eight).

200 millions transistors will probably a good guess number for this current cell (give or take). That is one PU and several SPUs plus controllers.

For PS3, depends on their time table, IF they used 90nm for launch its most likely use this current version of cell and 200+ mil transistors GPU from NV. By the time they shift to 65nm, the NV GPU will be integrated into cell and be on a single chip, maybe after several revision.

[passerby]

I ought to knock my own head. Someone's been posting links to Stanford's stream processor and I never looked at it till now. The number of similarities are uncanny - '8 ALU clusters to a processor', 'each cluster running on a kernel', etc. Plus, one of the ISCC papers titled 「26.7 A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor」jointly presented by Rambus and Stanford. The programming model is also described, though I would have prefered more details. Great read.

[GwymWeepa]

I ought to knock my own head. Someone's been posting links to Stanford's stream processor and I never looked at it till now. The number of similarities are uncanny - '8 ALU clusters to a processor', 'each cluster running on a kernel', etc. Plus, one of the ISCC papers titled 「26.7 A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor」jointly presented by Rambus and Stanford. The programming model is also described, though I would have prefered more details. Great read.

For those out there who are ignorant of what the heck that is, can someone give a summary of what a stream processor is and how that differs from a traditional CPU?

[passerby]

For those out there who are ignorant of what the heck that is, can someone give a summary of what a stream processor is and how that differs from a traditional CPU?
It is not a difficult read. http://cva.stanford.edu/imagine/

[nAo]

PU should have much more transistor than that, moreover one has to factor in L2 cache too! Maybe PS3 CPU will double local SPU sram too..
What about a 400-500 milion transistors count? ;)

[Megadrive1988]

PS3 CPU should be 500M transistors or more. maybe approaching a billion

[Tahir2]

PS3 CPU should be 500M transistors or more. maybe approaching a billion

From 500M transistors or more to maybe approaching a billion? You love to double your numbers and hedge your bets don't you Megadrive? ;)

[Squeak]

For those out there who are ignorant of what the heck that is, can someone give a summary of what a stream processor is and how that differs from a traditional CPU? http://www.beyond3d.com/forum/viewtopic.php?p=420155&highlight=stream#420155

[j^aws]

Here's an EE+GS die on 90nm,

http://homepage.mac.com/jabdin/.Pictures/Cell/EE-GS.jpg

FWIW, I had a go at a die area of a 4 CELL-BE with 64MB eDRAM on 65nm ~ 300mm2 :)

http://www.beyond3d.com/forum/viewtopic.php?p=353155#353155

Recent speculation suggest that SOI and eDRAM will not happen on the CPU but a GPU without SOI will have eDRAM.

If we had a hypothetical 4 CELL-BE that doesn't have eDRAM, I'd guestimate ~ 800 million transistors and with 64MB eDRAM ~ 1.3 billion. :P

[overclocked]

I must raise a question, as i understood the BE will be made on 65nm litho
and as Sony is fabbing the nV gpu also it should be on 65nm right?

[london-boy]

I must raise a question, as i understood the BE will be made on 65nm litho
and as Sony is fabbing the nV gpu also it should be on 65nm right?

That would be logical... But we'll have to see... Many logical options are not taken all the time...

[jvd]

I must raise a question, as i understood the BE will be made on 65nm litho
and as Sony is fabbing the nV gpu also it should be on 65nm right?

I dunno the state of sonys fabs but it could be that the cell chips will take up most of the production lines if not all of them , at least in the launch frame . Meaning the gpu would be made on an older line .

[nAo]

Meaning the gpu would be made on an older line .
Maybe ..or Maybe not. You should factor CPU and GPU yields too.

[jvd]

Meaning the gpu would be made on an older line .
Maybe ..or Maybe not. You should factor CPU and GPU yields too.

Right thats why i started off my post with this

I dunno the state of sonys fabs but it could be Note the use of dunno and could be .

[passerby]

That other GPU thread has a very sensitive title, so I'll post here instead. Didn't see this posted before.

http://www.gamesindustry.biz/content_page.php?aid=6025
Jen-Hsun Huang says how final silicon is expected by end of '05, plus the usual blah blah blah that we know. But the wording is original

"This next generation architecture took several hundred people several years to build, but this specific implementation of that architecture should take about 50 engineers. It's something we're running full throttle on," he added.

So yes, we have official info that it is a derivative of Nvidia's next-gen tech. However...

Huang also spoke of the PS3 chip's relationship with past PC-based architecture, or the lack thereof. "It's nothing to do with Windows, it doesn't use any of the Windows features, and it's not about driving Windows. It's not about the PC at all," he said of the GPU's background.

So the differing camps arguing in that other thread - all of you were right! Both camps! WOW! Have a merry christmas!

[j^aws]

That other GPU thread has a very sensitive title, so I'll post here instead. Didn't see this posted before.

http://www.gamesindustry.biz/content_page.php?aid=6025
Jen-Hsun Huang says how final silicon is expected by end of '05, plus the usual blah blah blah that we know. But the wording is original

"This next generation architecture took several hundred people several years to build, but this specific implementation of that architecture should take about 50 engineers. It's something we're running full throttle on," he added.

So yes, we have official info that it is a derivative of Nvidia's next-gen tech. However...

Huang also spoke of the PS3 chip's relationship with past PC-based architecture, or the lack thereof. "It's nothing to do with Windows, it doesn't use any of the Windows features, and it's not about driving Windows. It's not about the PC at all," he said of the GPU's background.

So the differing camps arguing in that other thread - all of you were right! Both camps! WOW! Have a merry christmas!

Ermm...that was already posted in that silly thread from hell...and subsequent silly comments made thereof! ;)

[passerby]

Well... :oops:

[j^aws]

Well... :oops:

Well, there have been around 100 pages of posts this month on the PS3...and technically, we still know JACK! :P

[loekf2]

Here's an EE+GS die on 90nm,

http://homepage.mac.com/jabdin/.Pictures/Cell/EE-GS.jpg



Yikes.... talking about a quick and dirty layout job ;-)

Someone just pasted the EE and the GS layouts next to each other.

In the semiconductors' industry we tend to like nice and rectangular layouts (usually fits better in a package), though in this case it goes into a BGA anyways so who gives a sh..

[version]

"Image rendering process for displaying three-dimensional image information on a two-dimensional screen "
SONY PATENT

http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=/netahtml/search-adv.htm&r=5&f=G&l=50&d=PTXT&p=1&S1=(sony+AND+proce ssor)&OS=sony+AND+processor&RS=(sony+AND+processor )

[SiBoy]

Yikes.... talking about a quick and dirty layout job ;-)

Someone just pasted the EE and the GS layouts next to each other.


It's smart. You want to re-floorplan that thing? :)